Tapeout Checklist

01Tapeout Signoff — Eight Phases

This checklist is organised into eight sequential phases covering the full backend execution cycle. The total timeline from RTL freeze to GDS submission is typically 4–8 weeks depending on design complexity.

02RTL Signoff Checklist

Confirm that the RTL is functionally complete, verified, and ready for synthesis. This is the last opportunity to make architectural changes.

1. 01
   [REQUIRED] RTL code freeze

   All RTL modifications are complete. No further functional changes after this point. Tag the RTL repository with a release tag (e.g., rtl_freeze_v1.0). Any post-freeze changes require a formal ECO process with re-verification.
2. 02
   [REQUIRED] Functional verification closure

   All testbench regressions pass at 100%. Coverage targets met: statement >95%, branch >90%, toggle >85%, functional coverage >95%. All known bugs resolved or documented as won't-fix with engineering justification.
3. 03
   [REQUIRED] Lint clean

   RTL passes lint checks (Spyglass, Ascent, or equivalent) with zero errors and zero warnings in the tapeout rule set. Waived warnings must be documented with engineering rationale. Focus areas: clock domain crossings, reset domains, undriven nets, width mismatches.
4. 04
   [REQUIRED] CDC/RDC verification

   Clock Domain Crossing and Reset Domain Crossing analysis is complete. All crossings use approved synchroniser structures. No metastability paths remain unresolved. CDC report reviewed and signed off by the design lead.
5. 05
   [RECOMMENDED] Formal verification (equivalence checking)

   Run formal equivalence checking between the RTL and the most recent spec model (if available). For safety-critical designs, formal property checking of critical assertions is strongly recommended.
6. 06
   [REQUIRED] Synthesis constraints ready

   SDC (Synopsys Design Constraints) file is complete and reviewed. Clock definitions, I/O delays, false paths, multicycle paths, and clock groups are defined. Constraints have been validated against the RTL timing intent document.
7. 07
   [REQUIRED] ROM code version freeze

   ROM code version confirmed and signed off by the design team. Re-generate all ROM modules with the final ROM code. Diff Verilog module (with hex file), CDL file, and GDS file against the tapeout version. CDL vs. GDS cross-check by the P&R team. Any mismatch must be resolved before proceeding.

03Synthesis Signoff Checklist

Confirm that the gate-level netlist meets timing, area, and power targets before starting physical implementation.

1. 01
   [REQUIRED] Synthesis timing clean at target frequency

   Post-synthesis timing analysis shows zero setup violations at the worst-case corner (e.g., SS 0.81V 125°C). Hold violations are expected at this stage and will be fixed during CTS. Setup slack should be positive with at least 5% margin for routing delay.
2. 02
   [REQUIRED] Gate-level simulation pass

   Run the full regression suite on the gate-level netlist with SDF back-annotation (if available). All tests that passed at RTL must pass at gate level. Mismatches indicate synthesis optimisation errors or constraint issues.
3. 03
   [REQUIRED] Area within floorplan budget

   Post-synthesis cell area fits within the target floorplan with standard cell utilisation ≤75% (for 28nm and below) or ≤80% (for 40nm and above). Higher utilisation causes congestion and timing closure difficulty during P&R.
4. 04
   [RECOMMENDED] Power estimation within budget

   Run power analysis on the gate-level netlist with representative switching activity (VCD or SAIF). Total power should be within the power budget defined at architecture stage. If power exceeds budget, consider clock gating improvements or voltage scaling.
5. 05
   [REQUIRED] DFT insertion complete

   Scan chains inserted. JTAG/boundary scan configured (if required). BIST for memories instantiated. DFT coverage target met (>95% stuck-at fault coverage). ATPG patterns generated and validated.
6. 06
   [REQUIRED] Lib file bus arrangement check

   Verify that all library files have bus arrangement from high address to low address. Incorrect bus ordering causes silent functional failures that will not be caught by DRC or LVS — only by simulation or in silicon.
7. 07
   [REQUIRED] Netlist hierarchy preservation

   Confirm that the P&R tool preserves the intended netlist hierarchy. Flattening critical hierarchies (e.g., clock generators, power domain controllers) can break ECO traceability and make post-silicon debug impossible. Verify hierarchy in the P&R database matches the synthesis output.

04Physical Design Checklist (P&R)

Floorplan, power integrity, special cell insertion, and structural checks specific to place-and-route. These items are checked before running final physical verification.

1. 01
   [REQUIRED] Floorplan consistency with approved version

   Final floorplan must be consistent with the approved V0.5 (or equivalent) floorplan. Macro placement, power domain boundaries, I/O ring, and die size confirmed against the floorplan review sign-off. Any deviation requires re-approval from the chip lead.
2. 02
   [REQUIRED] IR-drop & EM analysis pass

   Static IR-drop tolerance: VDD/VSS ≤10% of nominal supply, tightened to ≤6% for 40nm and below. Analysis conditions: 30% toggle rate (20% for 40nm and below), typical corner. EM reference temperature: 110°C. Both static and dynamic IR-drop must pass. Power grid modifications applied where violations exist.
3. 03
   [REQUIRED] Tapcell insertion (tapless libraries)

   If the standard cell library is tapless, verify that tapcells are inserted at the foundry-specified interval (typically every 15–25μm depending on process). Missing tapcells cause latch-up susceptibility that will not be caught by DRC but will cause field failures.
4. 04
   [REQUIRED] EndCap cell insertion

   Add EndCap filler cells (e.g., FILLER4BWP or equivalent) on both sides of every standard cell row. Mandatory for 28nm and below — these cells provide boundary OD continuity required by the foundry DRC rules. Missing endcaps cause DRC violations at row edges.
5. 05
   [REQUIRED] Decap cell insertion

   Insert decap cell arrays in available whitespace. Use larger cells (X2/X4 variants) where space permits — they provide better capacitance-to-area ratio than X1 cells. Decap cells reduce dynamic IR-drop and suppress supply noise. Verify decap placement does not block routing channels in congested areas.
6. 06
   [REQUIRED] Power-down block output isolation check

   For designs with power shutoff domains: verify that no outputs from a power-down block are left floating. Every output from a switchable domain must connect to an isolation (ISO) cell. Floating outputs from powered-down blocks cause crowbar current in the always-on domain and can damage the receiving logic.
7. 07
   [REQUIRED] Power switch (MTCMOS/PSO) cell check

   For on/off power domains: verify global power and local power (power_block_SW) connections are correct. Confirm PSO (Power Switch-Off) chain daisy-chain connectivity. Check header/footer switch cell sizing against the domain's peak current requirement.
8. 08
   [REQUIRED] Clock tree double spacing and shielding

   All clock tree nets must honour double-spacing routing rules. Apply shielding (VSS/VDD shield wires) for clock nets where required by the timing budget. Analog signal paths should be shielded upon designer request. Verify that the router does not violate double-spacing after optimisation passes.
9. 09
   [REQUIRED] Special clock path verification

   Manually verify the following clock paths: PLL reference clock input, PLL output clock distribution, and analog IP clock input/output connections. These paths are often excluded from CTS and require manual routing or special constraints. Incorrect PLL clock routing causes jitter that will not appear in STA but will fail in silicon.
10. 10
    [REQUIRED] Analog-digital interface check

    Verify all analog-digital boundary connections: signal routing, guard ring continuity, substrate isolation, and supply separation. Analog signals crossing digital routing channels must have proper shielding. Confirm that no digital clock/data lines route over sensitive analog blocks.
11. 11
    [RECOMMENDED] Spare cell placement

    Verify that spare cells are distributed evenly across the die. Spare cells (inverters, NANDs, NORs, flip-flops) enable post-silicon ECO fixes via metal-only mask changes. Typical density: 2–5% of total cell count. Record spare cell locations and types for the ECO reference document.
12. 12
    [RECOMMENDED] Special group/region placement check

    Verify that cells assigned to specific placement groups or regions (e.g., timing-critical clusters, datapath groups) are placed within their designated areas. Incorrect region assignment causes timing violations that are difficult to diagnose.
13. 13
    [REQUIRED] TCAD cell check

    If the foundry requires TCAD (Technology Computer-Aided Design) marker cells, verify they are placed at the required locations. This is foundry-specific — check the PDK release notes for TCAD cell requirements at your target node.

05Post-P&R Physical Verification Checklist

The most critical phase: LVS, DRC, ERC, and antenna verification with foundry runsets. Every item in this phase is a potential tapeout blocker. Record all waived violations in the remarks column of the signoff sheet.

1. 01
   [REQUIRED] Route forbidden region check

   Verify that no signal or power routes cross routing blockage areas (analog blocks, IP exclusion zones, seal ring regions). Route forbidden violations are Category A — any occurrence is a tapeout blocker.
2. 02
   [REQUIRED] Cross-voltage-domain connection check

   Verify that no high-voltage net connects to a low-voltage device. Cross-domain connections cause oxide breakdown and reliability failures. Check all power domain boundaries for correct level-shifter insertion.
3. 03
   [REQUIRED] Clock tree buffer cell verification

   Confirm that all clock tree cells are from the designated clock buffer/inverter library (CK-suffixed cells or equivalent). Non-clock cells in the clock tree have different delay tracking characteristics and will cause skew variation across PVT corners.
4. 04
   [REQUIRED] Don't-use cell audit

   Verify that no cells from the 'don't use' list appear in the final netlist. Don't-use cells are excluded by the foundry or library vendor due to reliability concerns, DFM issues, or model inaccuracy at the target node.
5. 05
   [REQUIRED] Don't-touch net and cell check

   Verify that all don't-touch nets and cells are preserved unchanged by the router and optimiser. Critical cells that must not be modified include: latch generators (lat_gen), clock gating cells (clk_gate), custom muxes (mux21), delay chains (DLY, mem_dly), scan mode nets (smi_sn), and chip ID cells. Any modification to these cells invalidates the associated verification.
6. 06
   [REQUIRED] Max-length path check

   Verify that no signal net exceeds the maximum length constraint. Excessively long nets cause signal integrity issues (crosstalk, delay) and may violate foundry-specific antenna rules. Flag any net exceeding the project's max-length threshold for review.
7. 07
   [REQUIRED] Stream in/out layer mapping verification

   Verify the GDS stream-in and stream-out mapping file matches the foundry's layer definition exactly. Layer number or datatype mismatches cause silent fabrication errors — the design will be built with the wrong physical intent on the affected layers.
8. 08
   [REQUIRED] Layout boundary check

   Verify that no geometry extends beyond the chip boundary (die outline). Out-of-boundary geometry causes reticle assembly errors in MPW and may overlap with adjacent designs in the shuttle.
9. 09
   [REQUIRED] GDS mask layer completeness check

   Verify that all required mask layers are present in the GDS export. Missing layers (e.g., via layers, implant layers, well layers) cause incomplete fabrication. Cross-reference the GDS layer list against the foundry's required layer table.
10. 10
    [REQUIRED] LVS clean — full options audit

    Run LVS with the foundry-specified runset. For low-power designs, the netlist must include power/ground pin connections (not just signal connectivity). Verify all LVS options before running: variable settings, LVS REPORT MAXIMUM (set to ALL), ERC MAXIMUM RESULTS ALL, LVS BOX definitions, EXCLUDE LAYER/AREA/CELL settings, device tolerance parameters. For 40nm: enable GATE_TO_PG_CHECK. Record the exact runset version used.
11. 11
    [REQUIRED] LVS edtext verification

    Verify all edtext (text label) placements: edtext release matches the LVS-clean run exactly. For bump designs: bump edtext must match the package team's coordinate file. No-bump edtext must be released and reviewed as part of the LVS-clean run. Verify that each edtext label is placed at the geometric centre of its corresponding bump.
12. 12
    [REQUIRED] LVS report and RVE review

    Review the full LVS report and RVE (Results Viewing Environment) database. Zero errors required. Any waived violations must be recorded with engineering justification in the signoff sheet remarks column.
13. 13
    [REQUIRED] Soft connections check

    Verify that all soft connections (partial connectivity through substrate or well ties) are intentional and documented. Unintentional soft connections are a common source of LVS mismatches that are difficult to debug.
14. 14
    [REQUIRED] ERC report and floating check

    Review the full ERC (Electrical Rule Check) report and RVE database. Zero unresolved errors. Specifically verify: no floating gates (gates connected to nothing or only to other gates without a discharge path), no floating wells, no unconnected I/O pins. Floating gate violations are Category A — they cause unpredictable switching behaviour in silicon.
15. 15
    [REQUIRED] ESD and latch-up check

    Verify complete ESD discharge paths from every I/O pad to the supply rails. Run the foundry's latch-up rule check. Confirm guard ring continuity around I/O cells and between NMOS/PMOS wells. ESD path incompleteness causes chip failure during handling or testing.
16. 16
    [REQUIRED] Substrate and well tie check

    Verify PSUB is not connected directly to ground where prohibited by the process. Confirm all N-tap cells connect to the correct ground net, and all P-tap cells connect to the correct power net. Record any waived violations.
17. 17
    [REQUIRED] CLP check with diode insertion verification

    Run the CLP (Charge-Loading Prevention / antenna) check. Pay special attention to diode insertion: verify that all antenna fix diodes are properly connected and that the diode insertion script has not placed diodes in incorrect locations (e.g., inside hard macros or across power domain boundaries).
18. 18
    [REQUIRED] DRC clean — full options audit

    Run DRC with the foundry's official runset (not the P&R tool's in-design deck). Verify all DRC options before running: variable settings, DRC MAXIMUM RESULTS ALL, EXCLUDE LAYER/AREA/CELL definitions, FULL CHIP mode (open), MIX SCHEME (off). Record the exact runset version. Zero violations required — waived violations need documented foundry approval.
19. 19
    [REQUIRED] DFM density checks (40nm and below)

    For 40nm and below: OD (oxide diffusion), PO (polysilicon), and metal layer densities must not exceed the foundry's maximum density requirement. Run the DFM-specific rule deck in addition to standard DRC. Verify dummy OD/PO fill is applied correctly. Verify dummy metal fill density per layer. Check that density violations in pad ring areas are resolved.
20. 20
    [REQUIRED] Off-grid geometry check

    Verify that all geometry is on the manufacturing grid. Off-grid vertices cause mask generation errors. Run the foundry's off-grid check as part of the DRC flow. Common sources of off-grid geometry: imported IP blocks with different grid resolution, analog layout drawn at sub-grid resolution.
21. 21
    [REQUIRED] DRC report and RVE review

    Review the full DRC report and RVE database. Zero unresolved violations. Record all waived violations with foundry-approved waiver documentation in the signoff sheet.
22. 22
    [REQUIRED] Antenna check clean

    Run the antenna rule check with the foundry's official antenna runset. Verify options: variable settings, DRC MAXIMUM RESULTS ALL, EXCLUDE LAYER/AREA/CELL. For 90nm/65nm/40nm: zero violations required — no waivers accepted for antenna violations at these nodes. Antenna diodes must be properly connected and verified by CLP.
23. 23
    [REQUIRED] Waiver list review and sign-off

    Compile the complete DRC/ERC waiver list. Each waiver must be reviewed by the analog owner and confirmed by the checker. The waiver list is a tapeout deliverable — the foundry or broker will audit it. Undocumented waivers are grounds for GDS rejection.
24. 24
    [CONDITIONAL] Metal-fix tapeout checks

    If this is a metal-fix (metal-only re-spin) tapeout: run LVL (Layout vs. Layout) comparison between the original and modified GDS to verify only intended layers are changed. Run RTO (Re-Tapeout) DRC on the modified layers only. Document the RTO DRC report path for reviewer access.

06Post-P&R Timing Signoff Checklist

Multi-corner timing analysis with extracted parasitics — the definitive check that determines whether the chip will meet frequency and power targets in silicon.

1. 01
   [REQUIRED] RC extraction verification

   Run parasitic extraction (StarRC, QRC, or equivalent) on the final routed design. Verify extraction settings: correct process corner files, correct temperature, correct metal stack definition. Cross-check extracted SPEF/DSPF file size and net count against the design database — significant discrepancies indicate extraction errors.
2. 02
   [REQUIRED] RC annotation coverage check

   Verify that RC annotation coverage is >99.5% of all nets. Unannotated nets use ideal (zero-delay) parasitics, which means timing violations on those nets will not appear in STA. Identify and resolve all unannotated nets before signing off timing.
3. 03
   [REQUIRED] OCV analysis (on-chip variation)

   Run STA with OCV derating enabled. For 40nm and below, use AOCV (Advanced OCV) or POCV (Parametric OCV) instead of flat OCV for more accurate modelling. Verify that OCV derating tables match the foundry's specified values for the target process. Flat OCV is acceptable for 65nm and above.
4. 04
   [REQUIRED] Multi-corner STA — zero setup violations

   Run static timing analysis across all signoff corners (minimum: SS/TT/FF; temperature: -40°C, 25°C, 125°C; voltage: nominal ±10%). Zero setup violations at all corners. Include extracted parasitics from the corresponding RC corner.
5. 05
   [REQUIRED] Multi-corner STA — zero hold violations

   Zero hold violations across all corners after hold fixing. Hold analysis must include CTS uncertainty and OCV derating. Pay special attention to clock domain crossing paths, asynchronous interfaces, and paths between power domains with different supply voltages.
6. 06
   [REQUIRED] Signal integrity (SI) analysis

   Crosstalk delay (delta delay) and crosstalk glitch analysis complete. No functional failures from crosstalk-induced glitches on clock or reset nets. Crosstalk delta delays included in the timing signoff. Critical nets with SI violations must be shielded or re-routed with increased spacing.
7. 07
   [REQUIRED] Power analysis signoff

   Final power analysis with post-route parasitics and representative switching activity (VCD/SAIF from gate-level simulation). Leakage power, dynamic power, and total power reported per power domain. Results must be within the power budget and within the package's thermal dissipation limits.
8. 08
   [RECOMMENDED] Post-layout simulation of critical paths

   Run SPICE or FastSPICE simulation with extracted parasitics on critical paths: PLL, high-speed I/O interfaces, analog blocks, and clock generators. Gate-level simulation with SDF back-annotation for the full regression suite is recommended but may be schedule-constrained.

07GDS Preparation & Submission Checklist

Final GDS export, foundry compliance verification, and handoff to the broker or foundry.

1. 01
   [REQUIRED] GDS export with verified layer mapping

   Export final GDSII using the foundry-specified layer map file (same mapping file verified in Phase 4). Verify all mask layers are present in the export. Run a GDS viewer to visually inspect the top cell and confirm bounding box dimensions match the die size.
2. 02
   [REQUIRED] GDS file integrity check

   Verify GDS file size matches the export log. Run CRC or checksum verification. Open the GDS in an independent viewer (Calibre DESIGNrev or KLayout) — not just the P&R tool — to confirm readability and layer completeness.
3. 03
   [REQUIRED] Cell name uniqueness verification

   Verify that your top-level cell name and all subcell names do not conflict with foundry-reserved names, broker assembly block names, or other MPW participants' designs. Use the cell naming prefix assigned during slot registration.
4. 04
   [REQUIRED] Submission package assembly

   Prepare the complete submission package: final GDS file, DRC/LVS/ARC/ERC clean reports, waiver documentation, cell name list, die size confirmation, pad/bump coordinate file, and any foundry-required submission forms. Record all EDA tool versions and runset versions used.
5. 05
   [REQUIRED] Submit before deadline with buffer

   Submit the complete package to the broker or foundry at least 2 business days before the GDS deadline. This buffer allows the broker to run their own DRC/LVS checks and flag issues for resolution. Late submissions are rejected without exception.
6. 06
   [RECOMMENDED] Pre-submission review with broker

   Schedule a pre-submission review call with the broker or VLSIShuttle to walk through the submission package, confirm cell naming, verify tile placement coordinates, and resolve any open items before the formal deadline.

08Packaging & Assembly Checks

Additional checks required for flip-chip, bumped, or RDL-based designs. Skip this phase if your design uses wirebond packaging with standard pad ring.

1. 01
   [REQUIRED] RDL metal density under bump

   For designs with redistribution layer (RDL): metal density under bumps must exceed 15% for the three outer bump rings and exceed 10% for inner bumps. Insufficient metal density under bumps causes bump delamination during reflow and reliability failures in the field.
2. 02
   [REQUIRED] L-mark (fiducial) placement

   For flip-chip designs: add fiducial L-marks on the AP (aluminum pad) layer or the final top metal layer. L-mark size and placement rules must follow the OSAT vendor's fiducial specification (e.g., SPRD_RDL_Fiducial_Rule). L-mark placement must be confirmed with the substrate designer.
3. 03
   [REQUIRED] Corner dummy exclusion

   Verify that no dummy fill is placed at the four die corners. Corner dummy fill interferes with wafer alignment and dicing. This is a common oversight when automated dummy fill is applied globally.
4. 04
   [REQUIRED] Seal ring verification

   Add the PR boundary with seal ring for flip-chip designs. Verify seal ring continuity around the entire die perimeter. Seal ring discontinuities cause moisture ingress and long-term reliability failures.
5. 05
   [CONDITIONAL] OD dummy layer check

   Verify that the OD (oxide diffusion) dummy layer is added where required by the process. This is process-dependent — some nodes require explicit OD dummy fill for stress uniformity.
6. 06
   [CONDITIONAL] ESD implant layer review

   Confirm that the ESD implant layer is correctly defined. This layer can be removed during manufacturing if not needed — verify with the foundry whether to include or exclude it in the final GDS based on your ESD protection scheme.

09Tool & Runset Version Control

Record all EDA tool and foundry runset versions used during the tapeout. This information is required for the submission package, for reproducibility in case of re-spins, and for foundry audit.

1. 01
   [REQUIRED] P&R tool version record

   Record the exact version of the P&R tool used (e.g., Synopsys IC Compiler II 2024.09, Cadence Innovus 23.1). Include any patches or hotfixes applied. Different tool versions may produce different routing and optimisation results.
2. 02
   [REQUIRED] RC extraction tool version record

   Record the exact version of the extraction tool (e.g., Synopsys StarRC 2024.09, Cadence QRC). The extraction tool version determines the accuracy of parasitic models and directly affects timing signoff quality.
3. 03
   [REQUIRED] STA tool version record

   Record the exact version of PrimeTime (or equivalent STA tool). Include the version of any add-on modules used (PrimeTime SI for signal integrity, PrimeTime PX for power).
4. 04
   [REQUIRED] Physical verification tool version record

   Record the exact version of the DRC/LVS tool (e.g., Siemens Calibre 2024.3, Synopsys IC Validator). Record separately: the tool version, the foundry DRC runset version, the foundry LVS runset version, and the antenna runset version. Runset version mismatches between your verification and the foundry's production check are a common cause of late-stage DRC failures.
5. 05
   [REQUIRED] PDK version record

   Record the exact PDK version, including any patches or updates applied during the project. Confirm that the PDK version matches the foundry's current production PDK. Deprecated PDK versions may have different device models or DRC rules that cause silent failures.

VLSIShuttle provides pre-tapeout engineering support — DRC/LVS checks, timing signoff review, and GDS assembly for MPW submissions. We can execute any phase of this checklist on your behalf.

11Top Causes of First-Silicon Failure

Based on real tapeout QA data across multiple foundries and process nodes, these are the most frequent causes of silicon failure and GDS rejection. Every item is preventable with systematic checklist execution.

• •
  LVS options misconfiguration

  Running LVS with incorrect variable settings, missing EXCLUDE CELL/AREA definitions, or without GATE_TO_PG_CHECK enabled at 40nm. The LVS passes locally but fails the foundry's production run with different options. Always audit every LVS option against the foundry reference before the final run.

• •
  IR-drop underestimation at advanced nodes

  Using 10% VDD/VSS tolerance at 40nm and below instead of the required 6%. Using 30% toggle rate instead of the required 20%. These seemingly small parameter differences cause the IR-drop analysis to miss real voltage droop problems that only appear during worst-case switching in silicon.

• •
  Missing endcap cells at 28nm and below

  Forgetting FILLER4BWP (or equivalent) endcap cells at row boundaries. At 28nm and below, endcap cells are mandatory for OD continuity — without them, the foundry DRC will reject the GDS, or worse, the design passes DRC but has yield issues due to stress effects at row edges.

• •
  Don't-touch cell modification by optimiser

  The P&R tool's post-route optimisation pass modifies or removes cells that should be preserved (clock gating cells, delay chains, latch generators, chip ID cells). This silently breaks functionality. Always verify don't-touch cell preservation after every optimisation run.

• •
  Stream mapping layer mismatch

  GDS stream-in or stream-out using an incorrect or outdated layer mapping file. The design looks correct in the P&R tool but has wrong physical layers in the fabricated wafer. Always verify the mapping file version against the foundry's current layer definition before final GDS export.

• •
  Power-down block floating outputs

  Outputs from a switchable power domain that are not connected to isolation cells. When the domain powers down, these outputs float to an undefined voltage, causing crowbar current in the always-on domain. This failure mode only manifests during power-state transitions and is extremely difficult to debug in silicon.

• •
  DFM density violation at 40nm and below

  OD, PO, or metal density exceeding the foundry maximum. Standard DRC may pass, but the DFM-specific density check fails. At 40nm and below, dummy OD/PO and dummy metal fills must be applied and verified separately from standard DRC. Density violations cause yield loss due to CMP (Chemical-Mechanical Polishing) non-uniformity.

• •
  Bump edtext coordinate mismatch

  For flip-chip designs: the edtext labels in the GDS do not match the package substrate designer's bump map. This causes the die to be packaged with incorrect bump assignments — a catastrophic failure that is only caught during package-level testing. Always cross-check edtext coordinates with the package team before GDS submission.

12Tapeout Timeline — From RTL Freeze to GDS Submission

Reference timeline for a medium-complexity SoC (500K–2M gates, 2–4 power domains, 10–20 IP blocks) targeting an MPW shuttle.

Need the complete backend execution cycle — from synthesis through GDS submission? VLSIShuttle handles the entire tapeout process for your design.

14Frequently Asked Questions

How long does the tapeout process take from RTL freeze to GDS submission?

For a medium-complexity design (500K–2M gates), expect 6–8 weeks from RTL freeze to GDS submission. Simple designs (under 500K gates, single power domain) can be done in 4–5 weeks. Complex designs (over 2M gates, multiple power domains, flip-chip packaging) may require 8–12 weeks. The critical path is usually physical verification iteration — resolving the last few DRC/LVS issues typically takes longer than expected.

What is the most common reason for tapeout delay?

LVS and DRC iteration at the physical verification phase (Phase 4). Common blockers include: LVS options misconfiguration that only surfaces during the foundry runset check, DFM density violations at 40nm and below, and late-discovered ERC floating gate issues. Timing closure at advanced nodes is the second most common cause. Both are preventable with this checklist's systematic approach.

What LVS options are most commonly misconfigured?

The most frequently missed options are: (1) GATE_TO_PG_CHECK not enabled at 40nm — this catches gate-to-power/ground shorts that standard LVS misses, (2) EXCLUDE CELL or EXCLUDE AREA settings that inadvertently skip verification of critical blocks, (3) LVS REPORT MAXIMUM not set to ALL, which causes the tool to stop reporting after a fixed number of errors and mask the true error count, and (4) incorrect variable settings for process-specific device recognition.

Do I need the packaging checks (Phase 7) for wirebond designs?

Phase 7 is primarily for flip-chip and RDL-based designs. For standard wirebond packaging with a conventional pad ring, you can skip Phase 7. However, you should still verify seal ring integrity and confirm that your pad ring cells are from the correct I/O library version for your target process.

Can VLSIShuttle handle the entire tapeout process?

Yes. VLSIShuttle provides end-to-end backend execution — from post-synthesis netlist through physical design, verification, timing signoff, GDS preparation, and foundry submission. We execute every item on this checklist using foundry-qualified tool flows and PDK environments. We maintain current versions of ICC II, StarRC, PrimeTime, and Calibre with up-to-date foundry runsets. Contact us with your design specification for a scope and timeline estimate.

15Related Resources

• TSMC MPW Schedule 2026

  Shuttle deadlines, supported nodes, and submission guide for TSMC MPW runs in 2026.
• MPW Cost Estimation

  Reference pricing by foundry and process node. Estimate your total prototyping budget.
• IC Tapeout Guide

  Educational overview of the IC tapeout process for teams new to silicon.
• ASIC Design Flow

  Complete ASIC design flow from RTL through backend implementation.
• IC Backend Services

  Physical implementation from netlist to GDSII — DRC/LVS closure, timing signoff, foundry submission.
• Scan Chain ECO Case Study

  How we inserted 130 registers into finalized scan chains post-route without breaking timing or rerunning DFT.

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   Taiwan Semiconductor Manufacturing Company
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   EUROPRACTICE / imec
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   Synopsys
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   Siemens EDA