The Complete IC Tapeout Guide

Tapeout is the critical milestone when your IC design is finalized and submitted for fabrication. This guide covers everything you need to know for a successful tapeout.

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Understanding Tapeout

01What is IC Tapeout?

IC tapeout (or chip tapeout) is the final step of the design phase where the completed GDSII database is delivered to the foundry for mask manufacturing and wafer fabrication. The term originated when designs were literally output to magnetic tape.

Point of No Return: Once taped out, changes require new masks ($100K-$10M+) and restart fabrication. Every issue must be caught before tapeout.
GDSII Delivery: The final deliverable is a GDSII (or OASIS) database containing all mask layers. This file defines exactly what will be manufactured.
Foundry Sign-Off: The foundry verifies your design meets their manufacturing rules before committing to production.

Pre-Tapeout Verification

02Tapeout Checklist

Essential checks before submitting your design for IC tapeout.

•
DRC Clean
Design Rule Check must pass with zero violations. Every DRC error risks manufacturing defects or yield loss.
•
LVS Clean
Layout vs Schematic verification confirms the physical layout matches the intended circuit. No LVS errors allowed.
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ERC Clean
Electrical Rule Check catches issues like floating gates, antenna violations, and well connectivity problems.
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Timing Signed Off
Static Timing Analysis must pass across all PVT corners. No setup/hold violations in sign-off conditions. Note: Clean STA reports don't always guarantee silicon robustness—see our SMIC 55nm timing case study for real-world lessons.
•
Power Verified
IR drop analysis confirms power grid adequacy. EM checks verify current density within limits.
•
Metal Fill Added
Density rules require metal fill patterns. Missing fill causes CMP issues and potential yield loss.

Workflow

03Tapeout Process Steps

The typical IC tapeout workflow from final verification to foundry submission.

01
Design Freeze
Lock RTL and stop functional changes. Only critical bug fixes allowed after this point.
02
Final Verification
Complete all sign-off checks: timing, power, DRC, LVS, ERC, antenna. Document any waivers.
03
GDSII Generation
Stream out final GDSII with all layers. Verify file integrity and layer mapping.
04
Frame & Marks
Add seal ring, alignment marks, and any required identification text or logos.
05
Final DRC/LVS
Run sign-off verification on merged GDSII. This is the last chance to catch issues.
06
Foundry Submission
Upload GDSII to foundry portal with supporting documentation. Confirm acceptance.

04Common Tapeout Issues

Problems frequently discovered during tapeout and how to avoid them.

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Last-Minute ECOs

Engineering Change Orders close to tapeout risk introducing new bugs. Freeze design early and resist changes.

•

Missing Metal Fill

Forgetting fill insertion causes density violations. Always run fill as part of standard flow.

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Antenna Violations

Long metal routes during fabrication can damage gates. Add antenna diodes during routing.

•

I/O Rule Violations

I/O cells have special rules for ESD protection. Verify I/O placement meets all requirements.

•

Real-World Timing Failure Case

A SMIC 55nm mixed-signal project passed static timing analysis at all corners with comfortable margins. Silicon came back functional but revealed timing-related inconsistencies under specific test patterns. Root cause: consecutive delay cell clustering created cumulative slew degradation that standard corner analysis didn't capture. Relaxed transition constraints allowed borderline signal integrity. A targeted ECO with tighter transition limits and spacing enforcement resolved the issue. The lesson: timing clean at signoff doesn't guarantee silicon robustness. See our detailed SMIC 55nm timing issue case study.

05IC Tapeout FAQ

Frequently asked questions about the tapeout process.

What is IC tapeout?: IC tapeout is the process of finalizing an integrated circuit design and submitting the GDSII database to a semiconductor foundry for manufacturing. It marks the transition from design to fabrication.
Why is it called 'tapeout'?: The term originated in the 1970s-80s when designs were output to magnetic tape for delivery to the foundry. Though we now use electronic file transfer, the name persists.
How long does tapeout take?: The tapeout process itself (final verification to submission) typically takes 1-2 weeks. However, reaching tapeout-ready status requires months of design and verification work.
What happens after tapeout?: The foundry creates photomasks from your GDSII (2-4 weeks), then fabricates wafers (6-12 weeks). Total time from tapeout to chips is typically 8-16 weeks.
Can I fix bugs after tapeout?: Only through a 'respin' - creating new masks and restarting fabrication. This costs $100K-$10M+ depending on the process node. Metal-only fixes (ECO) are cheaper but limited.
What files are needed for tapeout?: Primary deliverable is GDSII (or OASIS) database. Supporting files include layer mapping, design notes, test patterns, and sometimes timing/power databases.

Ready for Tapeout?

Submit your design through our MPW shuttle service for cost-effective fabrication.

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References

[1]
TSMC Tapeout Services
Taiwan Semiconductor Manufacturing Company
[2]
GlobalFoundries Design Services
GlobalFoundries
[3]
Siemens Calibre Physical Verification
Siemens Digital Industries Software
[4]
GDSII Stream Format
Semiconductor Engineering

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