TSMC MPW Shuttle Schedule 2026

01What Is the TSMC MPW Shuttle Service?

TSMC's Multi-Project Wafer (MPW) program allows multiple design teams to share a single reticle and split the fixed mask cost — reducing prototype fabrication cost by 80–95% compared to a dedicated wafer run.

02TSMC MPW Shuttle Schedule 2026 — Reference Windows

Approximate GDS submission deadlines for TSMC MPW shuttles in 2026. Exact dates are set by the broker and may shift by 1–2 weeks. Contact VLSIShuttle to confirm current availability and register intent.

• •
  Slot availability: TSMC MPW slots are allocated on a first-registered basis. Popular nodes (28nm, 40nm) at key windows fill weeks before the GDS deadline. Register intent at least 6 weeks before the target deadline.
• •
  IP freeze vs. GDS deadline: The GDS deadline is the foundry's final submission date. Your internal IP freeze should be at least 10 working days earlier to allow pre-tapeout checks, DRC sign-off, and GDS assembly.
• •
  Date confirmation: The dates above are derived from historical TSMC shuttle cadence and broker partner schedules. TSMC adjusts windows based on production capacity. All dates must be confirmed with VLSIShuttle or your broker before committing to a tapeout plan.

03TSMC Process Nodes Available in 2026 MPW

TSMC's MPW programme covers a range of CMOS and specialty nodes. Node availability per shuttle varies; not every node is offered in every run. Below is the 2026 lineup we actively coordinate.

• •
  180nm / 130nm (HV/RF variants available)

  High-volume mature nodes with multiple specialty variants including HV (high-voltage), RFCMOS, and embedded flash. Available in most quarterly shuttles. Largest tile area allocation.

• •
  90nm / 65nm LP/GP

  Low-power and general-purpose variants. 65nm is a common node for mixed-signal and RF designs targeting IoT and connectivity applications.

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  40nm LP / 40nm G

  One of the most cost-effective nodes for digital-intensive SoC prototyping. Strong EDA ecosystem, well-characterised PDK. Offered in all main quarterly runs.

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  28nm HPC / HPM / HLP

  High-performance compact and high-leakage-prevention variants. Requires 28nm-qualified PDK setup; DRC deck is more complex. IP freeze should be 3 weeks before GDS deadline.

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  16nm FinFET Compact (16FFC)

  Limited MPW availability. FinFET-based node requires separate PDK access agreement and TSMC qualification review. Contact VLSIShuttle for 16nm slot enquiries.

• •
  Specialty: RF, HV, eFlash, BCD

  TSMC also offers specialty variants at 180nm and 130nm for RF/mmWave, high-voltage power management, embedded flash, and BCD processes. These run on separate shuttle schedules. Enquire for availability.

04Engineering Checklist Before TSMC MPW Submission

Complete these steps in sequence before the GDS deadline. Missing any item is grounds for slot rejection by the foundry or broker.

1. 01
   Confirm PDK version and DRC deck

   Obtain the correct PDK release from your broker. TSMC updates PDK decks periodically; using a deprecated release will cause DRC failures at submission. Verify the active rule deck version with VLSIShuttle before beginning layout.
2. 02
   Complete DRC to zero violations

   Run the TSMC-specified DRC deck in full batch mode. Zero DRC violations is required. Waived violations must be documented with foundry-approved waiver forms. Unchecked DRC errors are the leading cause of slot rejection.
3. 03
   LVS clean against final netlist

   LVS must be run with extracted layout vs. the post-synthesis or hand-crafted schematic netlist. Ensure device models, bulk connections, and guard-ring connections are consistent. LVS shorts and opens must all be resolved — no unexplained differences.
4. 04
   Antenna rule check (ARC)

   Run the antenna rule check using the TSMC antenna deck. Metal antenna violations cause gate oxide damage during fabrication. All violations must be fixed by adding antenna diodes or routing changes — not by waivers.
5. 05
   ERC and density checks

   Run electrical rule check for floating wells, unconnected pins, and ESD paths. Verify metal fill density meets TSMC's min/max density requirements per layer. Automated fill is typically applied by the broker during GDS assembly, but your design must be fill-compatible.
6. 06
   GDS export and layer mapping verification

   Export final GDS using the TSMC layer map. Verify the exported GDS with a layer-by-layer inspection tool (Calibre DESIGNrev or equivalent). Confirm cell names do not conflict with TSMC reserved cell names or broker-level block names.

05Common TSMC MPW Submission Pitfalls

These are the most frequent reasons for slot rejection or first-silicon failure observed across MPW engagements. All are avoidable with a systematic pre-tapeout process.

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  Wrong PDK revision

  Submitting GDS built against an obsolete PDK version. TSMC's DRC checker at the broker level will flag mismatches. Always confirm the live PDK version before opening layout.

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  Missing or incorrect I/O ring

  Designs submitted without a compliant pad ring, or with pad ring cells from the wrong process variant. Verify which I/O library version is authorised for the target node and run.

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  ESD path incompleteness

  ESD protection networks that pass LVS but fail to provide complete discharge paths in the assembled chip context. Run ESD simulation or use TSMC's ESD reference design guidelines for pad ring construction.

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  Undocumented DRC waivers

  Attempting to submit designs with DRC violations without the TSMC waiver process. Brokers will reject GDS with unexplained DRC errors. Waivers require explicit foundry engineering review and approval.

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  Cell name collisions

  Using standard cell or IP block names that collide with broker-managed assembly blocks or other participants' top-level cell names. Use a unique top-cell prefix specified by the broker during slot registration.

• •
  Late IP freeze

  Underestimating the time between design freeze and GDS submission. DRC, LVS, ARC, and GDS export typically require 5–10 working days. Starting checks after the deadline has passed is the most common cause of missing a shuttle.

06TSMC MPW Cost Reference for 2026

MPW pricing depends on die area, process node, and the broker or access programme used. The figures below are 2026 reference ranges from EUROPRACTICE and comparable access programmes. Actual quotes depend on die size and current run allocation.

Send node, die size, and target window for a formal quote within 48 hours. Or use the MPW cost calculator for a first-pass estimate.

08How VLSIShuttle Coordinates TSMC MPW Slots

The typical engagement flow from initial enquiry to wafer delivery for a TSMC MPW run coordinated by VLSIShuttle.

1. 01
   Intent registration and slot reservation

   We register your design intent with the relevant TSMC broker (EUROPRACTICE, CMP, or regional partner), secure a tile allocation in the target shuttle window, and confirm the GDS deadline and cell naming requirements.
2. 02
   PDK provisioning

   We provision the correct TSMC PDK release for your process node under an NDA-protected transfer. This includes the DRC/LVS rule decks, model files, I/O library, and GDSII layer map.
3. 03
   Pre-tapeout check support

   We run pre-tapeout DRC, LVS, and ARC checks on your submitted GDS using the foundry-qualified environment. We return a clean check report or a structured error list with resolution guidance.
4. 04
   GDS assembly and submission

   We assemble your tile into the broker's reticle frame, apply required metal fill (broker-level), apply cell naming convention, and submit the assembled GDS to the foundry ahead of the deadline.
5. 05
   Fabrication tracking and liaison

   We monitor the lot through wafer fabrication and dice/sort stages, provide milestone updates, and escalate any foundry-flagged issues on your behalf.
6. 06
   Die delivery and incoming inspection

   We receive the diced lot, perform incoming inspection, and coordinate domestic or international courier delivery of die to your facility. Optional bare-die or packaged delivery available.

Need the complete backend execution cycle — from PDK setup through DRC/LVS closure and GDS submission? See our IC backend execution services or read the complete MPW shuttle guide.

10Frequently Asked Questions

How do I book a TSMC MPW slot for 2026?

TSMC does not sell MPW slots directly to most customers. Access is through authorised brokers such as EUROPRACTICE, CMP, or MOSIS, or through a coordination service such as VLSIShuttle. Contact VLSIShuttle with your target node, die size, and preferred shuttle window, and we will register intent and confirm slot availability with the relevant broker.

How far in advance do I need to register for a TSMC MPW shuttle?

For popular nodes (28nm, 40nm), register intent at least 6–8 weeks before the GDS deadline. Slots fill on a first-reserved basis. For mature nodes (180nm, 130nm), 4–6 weeks is typically sufficient, though earlier is always safer. 16nm slots require a longer lead time and a separate qualification discussion.

What is the minimum die size for a TSMC MPW tile?

TSMC's standard MPW tile allocation is typically a fixed tile size (e.g., 1×1mm, 2×2mm, or 3×3mm) per participant, depending on the shuttle configuration. You pay for the allocated tile area regardless of how much of it your design uses. There is no practical minimum design size — but minimum tile dimensions apply. VLSIShuttle can advise on the exact tile options for your target window.

Can I submit IP blocks from third-party vendors in a TSMC MPW GDS?

Yes, provided the IP is qualified for the target TSMC process node and the vendor has authorised its use under the PDK licence terms. Hard IP (SRAM, PLL, PHY) must be in GDSII form and pass DRC under the TSMC rule deck. Encrypted IP that cannot be DRC-checked directly must have a foundry-approved DRC waiver documentation package.

What happens if my TSMC MPW GDS is rejected by the foundry?

Foundry rejection is rare if pre-tapeout checks are completed correctly. If a GDS is rejected, the broker provides an error report. Minor issues (rule violations, naming conflicts) can sometimes be corrected and resubmitted within the window. Major DRC or completeness failures will cause the slot to be missed, and the next available window must be targeted. VLSIShuttle's pre-tapeout checks are specifically designed to prevent foundry-level rejection.

How long does it take from GDS submission to die delivery for TSMC MPW?

Typical end-to-end cycle time from GDS submission to die delivery is 12–16 weeks for mature nodes (180nm, 130nm, 65nm). For 40nm, expect 14–18 weeks. For 28nm, 16–20 weeks is common. 16nm FinFET has longer cycle times due to advanced process complexity. Exact timing depends on the foundry's current production loading.

Does TSMC MPW support mixed-signal and RF designs?

Yes. TSMC offers MPW access for mixed-signal designs at 180nm and 130nm RFCMOS nodes. These nodes include characterised RF models and specific DRC rules for RF layouts (guard rings, spiral inductors, transmission lines). Mixed-signal designs require careful LVS with substrate coupling modelling. VLSIShuttle has coordinated mixed-signal MPW submissions across multiple TSMC RFCMOS nodes.

11Related Resources

• Complete MPW Shuttle Guide

  End-to-end explanation of MPW services — how cost sharing works, what to expect, and how to choose a process node.
• MPW Cost Calculator

  Estimate die cost for a given process node and area. Covers TSMC, SMIC, GF, and UMC reference pricing.
• IC Backend Execution Services

  Physical implementation from netlist to GDSII. We cover DRC/LVS closure, multi-corner signoff, and foundry submission.
• Execution Record

  Track record of IC backend and MPW coordination engagements across foundries and process nodes.
• TSMC 28nm High-Speed Interface Postmortem

  First-hand account of timing closure at 800MHz on TSMC 28nm under MPW shuttle deadline constraints.

1. [1]
   TSMC Multi-Project Wafer (MPW) Service

   Taiwan Semiconductor Manufacturing Company
2. [2]
   EUROPRACTICE IC Service — MPW Access

   EUROPRACTICE / imec
3. [3]
   MOSIS Fabrication Service — TSMC Access

   MOSIS / USC