Understanding Semiconductor Wafer Fabrication

01What is Wafer Fabrication?

Wafer fabrication (also called wafer fab or simply fab) is the manufacturing process used to create integrated circuits (ICs) on semiconductor wafers. The semiconductor wafer fabrication process involves hundreds of individual steps performed in ultra-clean environments, transforming bare silicon wafers into complex chips containing billions of transistors.

The Silicon Wafer

Wafer fabrication begins with high-purity silicon wafers, typically 200mm (8-inch) or 300mm (12-inch) in diameter. These wafers are sliced from silicon ingots grown using the Czochralski process, achieving 99.9999999% (nine nines) purity.

Front-End of Line (FEOL)

FEOL processing creates the active devices (transistors) on the wafer. This includes gate oxidation, ion implantation for doping, and forming the transistor structures that perform computing operations.

Back-End of Line (BEOL)

BEOL processing creates the metal interconnects that wire transistors together. Modern chips have 10-15+ metal layers, with advanced processes using copper wires just nanometers wide to connect billions of transistors.

02Wafer Fabrication Steps

The silicon wafer fabrication process consists of several key stages, each repeated multiple times to build up the layers of the integrated circuit.

1. 01
   Oxidation & Deposition

   Thin films are grown or deposited on the wafer surface. Thermal oxidation creates silicon dioxide for insulation. CVD (Chemical Vapor Deposition) and PVD (Physical Vapor Deposition) add materials like polysilicon, metals, and dielectrics.
2. 02
   Photolithography

   Light-sensitive photoresist is coated on the wafer. UV or EUV light projects the circuit pattern through a mask onto the resist. The exposed pattern is developed, creating windows for the next process step.
3. 03
   Etching

   Material is selectively removed through the photoresist windows. Wet etching uses chemical solutions while dry etching (plasma) provides higher precision for advanced nodes. Pattern transfer creates the circuit features.
4. 04
   Ion Implantation

   Ions of dopant materials (boron, phosphorus, arsenic) are accelerated into the silicon to modify its electrical properties. This creates the n-type and p-type regions that form transistors.
5. 05
   CMP (Polishing)

   Chemical-Mechanical Polishing planarizes the wafer surface, creating a flat surface for subsequent layers. Critical for multi-layer metallization where each layer must be perfectly flat.
6. 06
   Metrology & Inspection

   Throughout the process, automated inspection systems check for defects. Critical dimension measurements ensure features match design specifications. Defective dies are mapped for later exclusion.

03Cleanroom Environment

Semiconductor wafer fabrication requires extraordinarily clean environments. A single particle can destroy an entire chip, making cleanroom technology essential.

ISO Class 1 Cleanrooms

Modern wafer fabs operate in ISO Class 1 cleanrooms with fewer than 10 particles per cubic meter larger than 0.1 micrometers. This is 10,000x cleaner than a hospital operating room.

HEPA & ULPA Filtration

High-Efficiency Particulate Air (HEPA) and Ultra-Low Penetration Air (ULPA) filters continuously remove particles. Air is completely replaced 10-600 times per hour in production areas.

Bunny Suits

Workers wear full-body cleanroom suits (bunny suits), gloves, and masks to prevent human contamination. Automated material handling systems minimize human presence in critical areas.

Water & Chemical Purity

Ultra-pure water (UPW) used in wafer fabrication contains fewer than 5 parts per billion of contaminants. All chemicals undergo rigorous purification before use in the fab.

04Lithography Technology

Lithography is the critical step that defines circuit patterns on the wafer. Advances in lithography have enabled the continued shrinking of transistor sizes.

Deep UV (DUV) Lithography

193nm ArF (Argon Fluoride) lasers are used for nodes down to 7nm (with multiple patterning). DUV systems cost $50-100M each and are workhorses for most wafer fabrication.

EUV Lithography

Extreme Ultraviolet (13.5nm wavelength) lithography enables sub-7nm nodes with single patterning. EUV machines cost $150M+ and are produced only by ASML. Essential for 5nm/3nm/2nm processes.

Multiple Patterning

For DUV at advanced nodes, multiple exposures and etches create features smaller than the light wavelength. Techniques like SADP (Self-Aligned Double Patterning) and SAQP (Quadruple) extend DUV capability.

05Process Node Evolution

Wafer fabrication technology has advanced through successively smaller process nodes, enabling more transistors per chip with each generation.

06Wafer Fabrication FAQ

Common questions about semiconductor wafer fabrication and the chip manufacturing process.

What is wafer fabrication?

Wafer fabrication is the process of manufacturing integrated circuits on semiconductor wafers. It involves hundreds of process steps including film deposition, photolithography, etching, ion implantation, and metrology. The process transforms a blank silicon wafer into thousands of individual chips (dies) containing transistors and interconnects.

How long does wafer fabrication take?

The wafer fabrication process typically takes 8-16 weeks from start to finish, depending on the process complexity and node. Advanced nodes with more metal layers take longer. This includes all processing steps but not packaging and testing, which add additional time.

How many process steps are in wafer fabrication?

Modern wafer fabrication involves 300-1000+ individual process steps, depending on the technology node. Each metal layer requires deposition, lithography, etch, and CMP steps. Advanced nodes with 10+ metal layers and complex transistor structures require more steps than mature nodes.

What is the difference between 200mm and 300mm wafers?

200mm (8-inch) and 300mm (12-inch) refer to wafer diameter. 300mm wafers have 2.25x the area of 200mm, allowing 2.25x more chips per wafer. Most advanced fabs use 300mm for efficiency, while 200mm fabs are common for mature/specialty processes. Industry is developing 450mm wafers.

Why are cleanrooms necessary for wafer fabrication?

Cleanrooms are essential because particles larger than the feature size can cause defects. At 7nm, a 0.1-micron particle is 14x larger than the smallest features. Cleanrooms maintain ISO Class 1-4 environments with sophisticated air filtration, temperature/humidity control, and strict protocols.

What is photolithography?

Photolithography is the process of transferring circuit patterns onto the wafer using light. A photomask containing the pattern is illuminated, projecting the image onto photoresist-coated wafers. The exposed resist is developed, creating windows for subsequent etching or deposition steps.

What is EUV lithography?

EUV (Extreme Ultraviolet) lithography uses 13.5nm wavelength light to pattern features for advanced nodes (7nm and below). The short wavelength enables smaller features than traditional 193nm DUV lithography. EUV machines cost $150M+ and are made exclusively by ASML.

How much does wafer fabrication cost?

Wafer fabrication costs vary dramatically by node. Processing a 300mm wafer costs: $2,000-$5,000 for mature nodes (65nm+), $5,000-$10,000 for mainstream (28nm-22nm), $10,000-$20,000 for advanced FinFET (16nm-7nm), and $20,000+ for leading edge (5nm and below). MPW shuttles share these costs among participants.

Ready to Fabricate Your Design?

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1. [1]
   SEMI Industry Standards

   SEMI - Semiconductor Equipment and Materials International
2. [2]
   TSMC Technology

   Taiwan Semiconductor Manufacturing Company
3. [3]
   ASML Lithography Technology

   ASML Holding
4. [4]
   Applied Materials Semiconductor Solutions

   Applied Materials