Execution Scope
We deliver backend implementation with tapeout accountability, including foundry coordination. PDK setup through mask submission — DRC/LVS closure, multi-corner signoff, and GDS handoff for teams that need silicon on schedule.
Shuttle Service
MPW Shuttle Coordination
We manage the full MPW slot lifecycle from process selection through GDS handoff and foundry acceptance. Customers deliver a DRC/LVS-clean netlist or GDSII; we handle PDK provisioning, pre-tapeout checks, slot registration, and mask submission across TSMC, SMIC, GlobalFoundries, and UMC programs.
- Foundry and process node selection
- PDK provisioning and DRC deck setup
- GDS submission and pre-tapeout checks
- Reticle slot registration and mask coordinates
- Fabrication tracking and foundry liaison
- Die delivery and incoming inspection
Typical deliverables: Foundry-accepted GDSII, diced die lot, optional bare-die or packaged delivery, tapeout acceptance confirmation
Foundry Agency
Tape-out Agency
Direct foundry coordination across TSMC, SMIC, GlobalFoundries, UMC, and HLMC. We handle NDA execution, PDK licensing, multi-foundry price comparison, and tapeout data freeze management — reducing coordination overhead for engineering teams without established foundry relationships.
- Foundry NDA and PDK licensing
- Multi-foundry quote and lead-time comparison
- Engineering change and ECO coordination
- Tapeout deadline and data freeze management
- IP protection and secure data transfer
- Wafer procurement and delivery coordination
Typical deliverables: Signed foundry contract, tapeout approval confirmation, wafer lot delivery, OSAT coordination on request
Backend Execution for Tapeout
IC Physical Implementation
Backend execution from synthesized netlist to tapeout-ready GDSII. We cover multi-corner/multi-mode signoff, PDK compliance, design-for-yield, and foundry submission package preparation. Engagements run under NDA; full ownership of all deliverables returns to the customer on completion.
- Floorplanning and power grid design
- Place and route (Cadence Innovus / Synopsys ICC2)
- Multi-corner, multi-mode timing signoff
- DRC/LVS closure and antenna rule check
- Parasitic extraction and SI analysis
- GDSII generation and tapeout package prep
Typical deliverables: Signoff-clean GDSII, timing/power/SI reports, LVS netlist, DRC-clean layout, foundry submission package
Execution Experience
8
Tapeouts delivered (last 24 months)
22–180nm
Node range
0
Silicon failures
10–14 wk
Typical backend cycle
Representative Tapeout Work
- 28nm TSMC — 1.8M-instance mixed-signal SoC, 6 clock domains, 800MHz SerDes interface
- 55nm SMIC — Sensor AFE with 12-bit ADC, OCV derating rebuild, first-pass silicon
- 40nm SMIC — IoT SoC, 3 voltage domains, UPF-based implementation
- 28nm ECO — 130-register scan chain insertion post-route, no full rerun
Discuss Scope
Send node, die size, and schedule. Initial response within 48 hours.