Scan Chain ECO After P&R: Inserting 100+ Registers Without Full Rerun

01Project Context

A 28nm digital SoC, roughly 2M instances, mixed-clock architecture with 6 clock domains. The design had passed timing signoff, DRC/LVS were clean, and scan ATPG patterns were validated. We were three days from GDSII handoff.

02Project Environment

Exact tool versions and design parameters for this engagement.

• •
  Process Node

  28nm HPC (High-Performance Compact), foundry standard cell library with 12-track cells.

• •
  Design Scale

  ~2M instances, 6 clock domains, 48 scan chains (post-DFT), mixed-signal IP integration.

• •
  Implementation Tools

  Innovus 21.1, Conformal 22.1, Modus 22.1 (ATPG), PrimeTime 2022.03 (STA signoff).

• •
  ECO Stage

  Post-route, post-CTS, post-timing-signoff. DRC/LVS clean. 3 days before GDSII handoff.

• •
  ECO Scope

  130 new flip-flops (94 sys_clk, 36 bus_clk), 4 hierarchical blocks, protocol state machine rework.

03Why This Is Harder Than It Sounds

Inserting registers into a finalized scan chain is not a simple netlist edit. Several constraints collide simultaneously.

• •
  Scan Order Is Physical

  After P&R, scan chain order reflects physical placement. The SI-to-Q connections follow routing topology. Inserting a register in the wrong position creates long-distance scan routing that causes hold violations and congestion.

• •
  Chain Lengths Are Balanced

  DFT tools balance chain lengths to minimize shift cycles. Adding 130 registers to a few chains creates imbalance—some chains become 20-30% longer than others. ATPG shift count increases, test time goes up, and some ATE patterns may exceed memory depth.

• •
  Clock Domain Mixing Is Forbidden

  Registers from different clock domains cannot share a scan chain segment. Mixing domains introduces capture conflicts during at-speed test. A single violation can invalidate the entire ATPG pattern set.

• •
  OCC Chains Must Be Excluded

  On-chip clock controller (OCC) scan chains are structurally fixed by the DFT architecture. These chains control test clock generation. Any modification risks breaking the test infrastructure entirely.

• •
  Timing Budget Is Zero

  The design is timing-closed. Every new scan connection is a new timing path. Long SI-to-Q routes add setup/hold risk on paths that were never part of the original timing analysis.

04Why Naive Approaches Fail

We have seen teams attempt quick fixes for scan chain ECO. These are the three most common mistakes and what actually happens.

• •
  Random Chain Insertion

  The simplest approach: append all new registers to the tail of arbitrary chains. This creates physical routes spanning the entire die—500um+ scan connections that violate hold timing, congest routing channels, and may not even be routable without ECO track expansion.

• •
  Single Chain Extension

  Some teams extend a single chain to absorb all new registers. The chain becomes 130 cells longer than its peers. Shift-cycle count increases for the entire test. On ATE with pattern memory limits, this can push the pattern set beyond capacity, requiring pattern re-compression or dropping coverage.

• •
  Ignoring Physical Distance

  Stitching registers purely by netlist proximity (same hierarchy, same module) without considering physical placement. Two registers in the same RTL module can be placed 400um apart after P&R. The scan connection between them becomes a timing and routing problem.

05Before vs After: Scan Chain Structure

Summary of scan chain state before and after ECO. The goal: absorb 130 new registers while keeping chain lengths balanced, routing local, and timing intact.

• •
  Key takeaway: 48 chains remained at 48 chains. No new scan I/O pins. No CTS re-run. The ECO was invisible to everything outside the scan SI/Q connections.

06Step 1: Logical Grouping by Domain and Edge

Before touching the netlist, we classified every new register along three axes.

1. 01
   Clock Domain Assignment

   Each register was tagged to its clock domain. In this design, the 130 registers fell into two domains: sys_clk (94 registers) and bus_clk (36 registers). No cross-domain stitching is allowed—this is the first hard constraint.
2. 02
   Clock Edge Separation

   Within each domain, registers were separated by active edge—posedge vs negedge. Mixing edges in a scan segment creates hold violations during shift because the capture windows are offset by half a cycle.
3. 03
   Hierarchical Block Mapping

   Each register was mapped to its physical hierarchical block. This determines which scan chains are candidates for insertion—only chains that already pass through that block's region.
4. 04
   OCC Chain Exclusion

   We identified all OCC-related scan chains and marked them as untouchable. These chains feed the on-chip clock controller and are structurally fixed. Any modification to an OCC chain would require re-validating the entire test clock architecture.

07Step 2: Physical-Aware Chain Insertion

With grouping done, we needed to decide exactly where in each chain to splice each register. The principle: minimize new routing.

1. 01
   Nearest Q-to-SI Point Matching

   For each new register, we identified the closest existing scan connection (Q-to-SI wire) in a compatible chain. "Closest" means physical distance in the placed design—not netlist hierarchy. We cut the existing Q-SI connection and inserted the new register between them.
2. 02
   Internal Sub-Chain Stitching

   When multiple new registers belonged to the same physical region and same domain, we first chained them together internally using S-shape routing to minimize wire length, then spliced the sub-chain as a single unit into the nearest existing scan segment.
3. 03
   S-Shape Routing Optimization

   Internal sub-chains were ordered using S-shape (serpentine) topology—alternating direction row by row—to keep all new scan wires short and local. This is the same principle DFT tools use during initial chain stitching, applied manually at ECO scale.
4. 04
   Congestion-Aware Track Selection

   Before committing each insertion point, we checked local routing congestion in Innovus. In two cases, the nearest Q-SI point was in a congested region, so we used the second-nearest point instead. An extra 15um of scan wire is better than a DRC violation.

08Step 3: Room-Based Scan Chain Redistribution

After insertion, chain lengths were unbalanced. Some chains gained 30+ registers while others gained none. We used a room-based redistribution strategy to rebalance.

1. 01
   Room Concept

   We defined physical 'rooms' corresponding to major placement regions in the floorplan. Each room contains a known set of scan chains passing through it. Redistribution only moves registers between chains within the same room—no cross-room scan connections.
2. 02
   Chain Length Target Calculation

   Target chain length = (total registers in room) / (number of chains in room). We calculated the delta for each chain and identified donors (chains longer than target) and receivers (chains shorter than target).
3. 03
   Tail-Transfer Redistribution

   From each donor chain, we detached registers from the tail end (physically furthest from scan-out) and appended them to a receiver chain that passes through the same physical region. This keeps scan wire lengths minimal while balancing chain counts.
4. 04
   Final Length Variance Check

   After redistribution, maximum chain length variance was under 5%. All chains stayed within the ATPG shift count budget. No chain exceeded ATE pattern memory limits.

09Step 4: Toolchain Execution and Validation

Manual planning, automated execution. Every step was scripted and validated through the standard tool flow.

1. 01
   Conformal ECO: Netlist Patch Generation

   Conformal ECO compared the pre-ECO and post-ECO netlists and generated the minimum-change patch. This included the 130 new registers plus all scan chain reconnections. The patch was reviewed line-by-line before application.
2. 02
   Innovus: Physical Implementation

   The ECO cells were placed using ecoPlace with manual coordinate guidance for the 14 registers that fell in congested areas. Scan connections were routed with ecoRoute. Total ECO routing impact: less than 0.3% of total route length.
3. 03
   Timing Closure Verification

   Incremental STA on all new and modified paths. Setup and hold were clean across all corners. Three paths required buffer insertion to fix hold—standard ECO-level adjustment. No path required re-optimization of existing logic.
4. 04
   ATPG Pattern Re-generation

   Full ATPG was re-run with the updated scan chain definitions. Stuck-at coverage: 99.2%. Transition coverage: 96.8%. Pattern count increased by only 2.1% compared to the pre-ECO baseline. No pattern exceeded ATE memory constraints.

10Results

The entire scan chain ECO—from receiving the functional patch to ATPG sign-off—was completed in 4 working days.

• •
  130 Registers Inserted

  All 130 new flip-flops fully integrated into scan chains across 2 clock domains and 4 hierarchical blocks.

• •
  Timing Preserved

  Zero setup violations. Three hold fixes (buffer insertion only). No existing timing path was disturbed.

• •
  No Full DFT Rerun

  Scan chain modifications were surgical. CTS was untouched. Clock tree latencies unchanged. Only scan SI/Q connections were modified.

• •
  Coverage Maintained

  Stuck-at: 99.2%. Transition: 96.8%. Pattern count increase: 2.1%. All within pre-ECO targets.

• •
  GDSII On Schedule

  Tape-out deadline met. The functional ECO did not push the schedule. Design was delivered to the foundry on the original date.

11What Most Teams Get Wrong

We have handled scan chain ECOs across multiple nodes. The pattern of failure is consistent.

• •
  Treating Scan as a Netlist Problem

  After P&R, scan chain stitching is a physical problem. Netlist-only reasoning—matching clock domains, appending to chain tails—ignores the routing consequences. Every scan connection is a physical wire with timing implications.

• •
  Underestimating Chain Imbalance

  Adding 50 registers to one chain and zero to adjacent chains seems harmless until ATE shift cycles increase and pattern memory overflows. Redistribution is not optional—it is a requirement for production-grade test.

• •
  Skipping Physical Validation

  Teams that insert scan registers without checking local routing congestion discover DRC violations during final signoff—the worst possible time. Congestion check before insertion takes minutes. Fixing DRC violations after routing takes days.

• •
  Not Automating the Flow

  Manual scan stitching for 10 registers is feasible. For 100+, it is error-prone. Scripting the grouping, insertion point selection, and chain reconnection is not overhead—it is the only way to ensure consistency across dozens of insertion points.

Facing a Late-Stage ECO with No Timing Margin?

If you have registers that need to be in scan chains but cannot afford a full DFT rerun, we can fix it. VLSIShuttle has executed post-route scan chain ECOs at 180nm, 130nm, 55nm, 40nm, and 28nm — physical-aware insertion, chain redistribution, and ATPG re-validation included. Send us your design spec and ECO scope. We will tell you if it is fixable without a full rerun, and how long it will take.

12Related Resources

More case studies and technical resources from our backend team.

• SMIC 55nm Timing Failure Recovery

  How clean STA reports missed delay cell clustering issues in silicon.
• TSMC 28nm High-Speed Interface Timing Closure

  800MHz interface timing convergence on a TSMC 28nm SoC.
• IC Tapeout Process Guide

  Complete tapeout flow from RTL to GDSII.
• Discuss Tapeout Scope

  Backend execution for ECO, timing closure, and DFT integration.

1. [1]
   Cadence Conformal ECO Designer

   Cadence Design Systems
2. [2]
   Cadence Innovus Implementation System

   Cadence Design Systems
3. [3]
   IEEE 1149.1 Standard for Test Access Port

   IEEE Standards Association