IC Backend Execution & Tape-out Responsibility
RTL freeze to foundry-accepted GDS — including ICC interface and mask submission coordination.
Foundry interface experience: SMIC / TSMC / UMC / Tower (project-specific, under NDA)
Scope of Accountability
What We Actually Own
Not fragmented. Not delegated. One accountable backend team.
01 Backend Discipline
Netlist handoff → signoff-ready GDSII
- Multi-corner signoff
- DRC/LVS closure
- IR/EM validation
- STA and physical verification
02 Tape-out & ICC Interface
GDS freeze → foundry-accepted mask
- PDK integration
- MPW coordination
- Mask package assembly
- Foundry submission and acceptance
03 ECO & Silicon Assurance
Late changes → incremental re-signoff
- Incremental re-signoff
- Late-stage timing control
- Post-layout validation
- Silicon debug support
Execution Record
8
Tape-outs (last 24 months)
22–180nm
Node coverage
3
Repeat clients
10–14 wk
Typical backend cycle
Representative Projects
- —28nm TSMC: 1.8M gates, 800MHz timing-critical interface
- —55nm SMIC: Sensor AFE with embedded ADC, first-pass success
- —110nm UMC: Analog-dominant power management controller
- —40nm SMIC: IoT connectivity SoC, multi-voltage domain
ICC Responsibility
Where We Differ from Design-Only Teams
Most backend teams stop at signoff. We manage the foundry interface.
- →Submission-ready DRC/LVS
- →MPW shuttle scheduling
- →Mask data preparation
- →GDS acceptance confirmation
Case Study
SMIC 55nm — Sensor AFE with Embedded ADC
Situation
Mixed-signal AFE with embedded 12-bit ADC. Customer had exited a previous backend engagement after persistent timing failures across temperature corners and a failed first silicon attempt. Deadline to SMIC shuttle window: 9 weeks.
What we did
Identified timing violations rooted in insufficient OCV derating for mixed-signal paths. Rebuilt constraint set with separate PVT corners for analog and digital domains. Full incremental re-signoff after each ECO cycle. ICC package assembled and submitted ahead of shuttle window with a one-week buffer.
Outcome
First-pass silicon success. All analog performance targets met on silicon. Customer re-engaged for 28nm follow-on project.
Tape-out Scope Review (Under NDA)
Send node, schedule, and scope. Initial technical feedback within 48 hours.