MPW Cost Estimation Guide

01Understanding the MPW Cost Model

MPW pricing is fundamentally area-based: you pay for the reticle tile area your design occupies. The per-mm² rate varies by foundry, process node, and access programme.

02MPW Cost per mm² by Foundry and Process Node

Reference price ranges for standard MPW tile allocation in 2026, derived from EUROPRACTICE programme data and comparable access channels. Prices are indicative and depend on die area, shuttle configuration, and current programme terms.

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  Price disclaimer: All figures are reference ranges derived from publicly available 2025 EUROPRACTICE programme data, MOSIS historical pricing, and VLSIShuttle's engagement experience. Actual pricing depends on die area, shuttle configuration, programme terms, and current availability. Always confirm pricing with VLSIShuttle or your access partner before committing to a tapeout plan.
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  Currency conversion: EUR/USD conversions use an approximate rate of €1 = $1.08. Exchange rate fluctuations will affect actual USD pricing for EUROPRACTICE-sourced shuttles.

03What Is Included in the MPW Price

A typical MPW engagement price includes multiple components. Understanding each helps you compare quotes accurately.

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  Tile allocation (reticle area)

  The dominant cost component — typically 60–70% of the total. This is the per-mm² charge for your design's area on the shared reticle. Standard tile sizes are 1×1mm, 2×2mm, 3×3mm, or 5×5mm depending on the foundry and shuttle configuration.

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  Mask and wafer fabrication

  Included in the tile price. The shared mask set cost is amortised across all participants in the shuttle run. The foundry runs a standard production lot (typically 25 wafers) and participants receive a proportional number of die.

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  Broker / access programme fee

  A flat or percentage-based fee charged by the access programme (EUROPRACTICE, CMP, MOSIS) for NDA management, PDK provisioning, GDS assembly, reticle integration, and die sorting. Typically 10–20% of the tile cost.

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  Die sorting and delivery

  The foundry dices the wafer lot and sorts die by participant tile. Bare die are packaged and shipped to the broker, who forwards to each participant. Delivery costs are usually included; expedited shipping is extra.

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  PDK access (if applicable)

  Some foundries charge a separate PDK licence fee, especially for advanced nodes. For TSMC 28nm and below, PDK access requires an NDA and may carry an annual fee through the broker programme.

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  Engineering services (optional)

  Pre-tapeout checks (DRC/LVS/ARC), backend implementation (P&R, signoff), and GDS assembly assistance are optional add-ons. VLSIShuttle provides these as separate service packages. Not included in the base MPW tile price.

04Estimating Your Die Area for Cost Planning

Your MPW cost is directly proportional to your die area. Estimating die area before layout completion requires understanding your design's gate count, memory requirements, and I/O pad ring.

05Hidden Costs That Affect Total Prototyping Budget

The tile price is only part of the total prototyping cost. Plan for these additional items when budgeting an MPW engagement.

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  Backend implementation engineering

  If your team does not have in-house physical design capability, you will need to outsource place-and-route, clock tree synthesis, and multi-corner timing signoff. For a 28nm design, backend implementation typically costs $30K–80K depending on complexity and turnaround requirements.

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  IP licensing

  Hard IP blocks (SRAM compilers, PLLs, SerDes PHYs, analog IPs) carry separate licensing costs from the foundry or third-party IP vendors. These are not included in the MPW tile price. Budget $5K–50K per IP block depending on the technology.

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  Packaging

  MPW delivers bare die. If your application requires packaged parts, you need to engage a packaging house (OSAT) separately. Wirebond QFN packaging for small lots (50–200 units) typically costs $5–15 per unit plus tooling ($2K–5K NRE). Flip-chip BGA is significantly more expensive.

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  Test programme development

  If production testing is required, you need an ATE test programme. Development cost for a basic mixed-signal test programme is $10K–30K. For complex SoC with high-speed interfaces, expect $30K–80K.

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  Re-spin risk

  First silicon success rate for MPW designs is approximately 60–75% depending on design maturity and verification depth. Budget for the possibility of a second shuttle run. The second run is typically faster and cheaper (same tile cost, but reduced engineering time), but it adds 4–6 months to your schedule.

Send your target foundry, process node, estimated die size, and preferred shuttle window. VLSIShuttle will return an itemised quote covering tile cost, broker fees, and optional engineering services within 48 hours.

07Choosing a Foundry for Cost-Optimised MPW

Foundry selection affects cost, lead time, and IP ecosystem. Here is a practical comparison for MPW cost optimisation.

08Strategies to Reduce MPW Prototype Cost

Practical engineering decisions that directly reduce your MPW engagement cost without compromising silicon quality.

1. 01
   Right-size your die area

   Die area is the single largest cost driver. Run floorplanning early to identify area-dominant blocks. Consider trading off SRAM size, I/O count, or analog resolution to reduce total die area by 20–30%, which directly translates to 20–30% cost reduction.
2. 02
   Choose the right process node

   Do not default to the most advanced node. A design that fits in 3mm² at 28nm might fit in 5mm² at 40nm — but the 40nm tile costs 40–50% less per mm². Run gate-count analysis to determine the minimum viable node for your performance requirements.
3. 03
   Use the earliest available shuttle window

   Last-minute shuttle registrations often incur rush fees or force you into a higher-priced broker channel. Planning 3–4 months ahead gives you access to the most cost-effective slots and avoids expedite charges.
4. 04
   Bundle engineering services

   Engaging VLSIShuttle for both MPW coordination and backend implementation typically costs less than sourcing separately. Bundled engagements avoid interface overhead and reduce total project risk.
5. 05
   Maximise first-silicon success rate

   A re-spin doubles your tile cost and adds 4–6 months. Investing in thorough pre-tapeout verification (DRC, LVS, timing signoff, post-layout simulation) is the highest-ROI spend in any MPW engagement. See the Tapeout Checklist for a systematic approach.

Need help estimating total prototyping cost for your specific design? VLSIShuttle provides complete cost analysis covering tile allocation, engineering services, IP licensing, and packaging.

10Frequently Asked Questions

How much does an MPW shuttle cost for a typical small design?

For a 2mm² die at 40nm through EUROPRACTICE, expect approximately $13,000–26,000 for the tile cost alone. Add broker fees (10–20%), and the total MPW engagement is typically $15,000–32,000 excluding optional engineering services. At 28nm, the same die size costs $26,000–32,000. At 180nm, $4,400–7,600. Use the reference table above for your specific foundry and node.

Why is there such a wide price range for the same node?

Price variation comes from several factors: (1) different access programmes charge different rates — EUROPRACTICE, CMP, and MOSIS have independent pricing, (2) shuttle configuration affects per-mm² cost — smaller shuttle runs with fewer participants cost more per tile, (3) tile size options vary — some shuttles offer fixed 2×2mm tiles while others allow custom sizing, and (4) demand-driven pricing — popular windows at popular nodes may carry premiums.

Is MPW more expensive than a dedicated wafer run?

No — MPW is dramatically cheaper. A dedicated mask set at 28nm costs $1–3 million. An MPW tile at 28nm costs $25,000–50,000. MPW achieves this 50–100× cost reduction by sharing the mask across multiple designs. The trade-off is that you receive fewer die (typically 40–100) and have no control over the production schedule.

Can I negotiate MPW pricing?

Direct price negotiation is limited for standard MPW programmes since rates are set by the access programme. However, you can reduce cost through: (1) choosing a less popular shuttle window, (2) reducing die area, (3) selecting a more cost-effective foundry, or (4) bundling multiple shuttle runs. VLSIShuttle can advise on the most cost-effective configuration for your requirements.

What is the cheapest way to get first silicon?

For absolute minimum cost, consider: (1) open-source PDK programmes like Google/SkyWater 130nm or IHP SG13G2, which offer free MPW access through programmes like Efabless, (2) academic access programmes if you qualify, or (3) mature-node shuttles at UMC or SMIC 180nm, which start at approximately $7,000–11,000 for a 3mm² die. Contact VLSIShuttle for guidance on the most cost-effective path for your specific design.

11Related Resources

• TSMC MPW Schedule 2026

  Shuttle deadlines, supported nodes, and submission guide for TSMC MPW runs in 2026.
• Tapeout Checklist

  Step-by-step signoff checklist from RTL freeze to GDS submission. Maximise first-silicon success rate.
• DPW Calculator

  Calculate dies per wafer and area utilisation for your die dimensions.
• MPW Pricing Guide

  Educational overview of how MPW pricing works and cost factors to consider.
• IC Backend Services

  Physical implementation from netlist to GDSII — DRC/LVS closure, timing signoff, foundry submission.

1. [1]
   EUROPRACTICE 2025 MPW Schedules & Prices

   EUROPRACTICE / imec
2. [2]
   MOSIS Fabrication Service

   MOSIS / USC
3. [3]
   Semiconductor Industry Association — IC Market Data

   SIA