Technical Reference

Engineering Knowledge Base

Guides and references for IC backend execution, tape-out coordination, and ASIC physical implementation.

Featured Technical Postmortem

SMIC 55nm — Sensor AFE Timing Failure Recovery

Inherited a failing backend engagement with persistent timing violations across temperature corners after a first-silicon failure. Rebuilt PVT corner strategy, re-signoff'd incrementally, and delivered to SMIC shuttle with one week buffer. First-pass silicon success.

55nm SMIC · Mixed-signal SoC · Clean STA, silicon timing failure, ECO recovery · First-pass success on respin

Tape-out & ICC

ICC execution, mask submission, and foundry coordination references

IC Tapeout Process Explained
End-to-end tapeout flow, ICC checklist, and foundry submission requirements
Complete MPW Shuttle Guide
Multi-Project Wafer services, cost sharing, shuttle windows, and participation
MPW Cost & Pricing Guide
Die size, process node, and foundry pricing factors for MPW runs
IC Tapeout Guide — Chinese Market
SMIC, HHGrace, and CXMT shuttle coordination for China-based projects
Open-Source MPW Programs
Free and subsidized fabrication programs for research and open hardware
TSMC MPW Shuttle Schedule 2026
Submission deadlines, supported nodes, pre-tapeout checklist, and slot coordination for TSMC MPW in 2026

ASIC Backend Discipline

Physical implementation, timing closure, and design methodology

ASIC Design Flow Explained
Synthesis through GDSII: placement, routing, timing closure, and signoff
What is ASIC Design?
ASIC vs FPGA trade-offs, design entry, and when custom silicon makes sense
Chip Prototyping Methods
Prototyping approaches, silicon validation, and iteration strategies
Wafer Fabrication Process
CMOS manufacturing steps, process node selection, and yield considerations
How Semiconductor Foundries Work
Foundry business model, PDK, capacity allocation, and qualification
ASIC Design Services Overview
Scope of professional backend services, engagement models, and deliverables

Project Postmortems

Project accounts and technical postmortems

SMIC 55nm — Timing Failure Recovery
How a clean STA report at signoff still caused silicon timing issues — and what it took to find and fix it.
TSMC 28nm — 800MHz Timing Closure
1.8M gate SoC with 800MHz interface domain. AOCV constraint rebuild, SI-aware closure, first-pass silicon under shuttle deadline.
SMIC 40nm — Multi-Voltage IoT SoC
Three-domain UPF-based implementation, voltage-aware signoff, and SMIC MPW coordination. On schedule, first pass.
ASIC Design Career Reference
Role definitions, toolchain expectations, and career progression in IC backend