VLSIShuttle
VLSIShuttle Backend Team
IC Backend Execution Specialists
Feb 28, 20267 min read
Case Study

TSMC 28nm High-Speed Interface: 800MHz Timing Closure Under Shuttle Deadline

Engineering postmortem on a 1.8M gate TSMC 28nm SoC with an 800MHz timing-critical interface. How structured PVT corner strategy and SI-aware signoff closed timing within a fixed shuttle window — first pass.

Discuss Your Backend Project
Background

01Project Context

We inherited the backend implementation midway through a 28nm TSMC project. The original team had completed floorplanning and initial placement, but timing closure had stalled at approximately 400 endpoints failing setup at the SS corner across the high-speed interface domain.

The design: 1.8 million gates, mixed-supply, with a high-speed serial interface domain clocked at 800MHz. The deadline to TSMC shuttle data freeze was 11 weeks from handoff.

At 28nm, OCV (on-chip variation) effects are significantly more pronounced than at 55nm or 110nm. The original timing constraint set used conservative global derating across all paths — causing over-pessimism that made real timing violations and false violations indistinguishable.

Root Cause

02The Timing Problem at 28nm

The stalled timing closure traced to three structural issues in how variation was being modeled.

  • •
    Global Derating Over-Pessimism

    Flat OCV derating applied uniformly meant paths through well-characterized macros and standard cells carried the same uncertainty as long cross-chip routes. The SS corner appeared ~12% more pessimistic than it should have been on characterized paths.

  • •
    SI Not Integrated in Closure Loop

    Signal integrity analysis was being run post-routing as a check, not as part of the iterative timing closure loop. At 800MHz, coupling-induced delay on the interface path was material — not a secondary effect.

  • •
    CTS Clock Skew Budgeting

    The 800MHz clock domain shared a CTS with lower-frequency blocks. Skew budgeting allocated margin from the high-speed domain to balance global skew — effectively tightening already-stressed interface paths.

  • •
    TSMC 28nm DFM Constraints

    TSMC 28nm has specific DFM requirements that introduced additional routing constraints on the high-density interface region, increasing congestion and coupling potential.

Our Approach

03Constraint Strategy Rebuild

Rather than incrementally patching failing paths, we rebuilt the constraint strategy for the interface domain from first principles.

  1. 01
    AOCV Corner Strategy
    Switched from global OCV derating to advanced OCV (AOCV) with depth-based derating tables provided in the TSMC 28nm PDK. Short local paths received tighter, accurate derating; long cross-chip paths retained conservative margins. This resolved ~60% of false violations immediately.
  2. 02
    SI-Aware Closure Loop
    Integrated PrimeTime SI into the closure loop. Every ECO iteration ran with coupling-delay annotation, not just in post-route checks. Critical interface nets were given explicit shielding constraints.
  3. 03
    Interface Domain CTS Isolation
    Separated the 800MHz interface clock domain from the lower-frequency shared CTS. Built a dedicated local clock tree with tighter skew budget. Recovered 35ps of effective setup margin across the critical path group.
  4. 04
    Incremental Physical Optimization
    Used ECO flow with targeted cell upsizing and minimal placement perturbation, preserving routing congestion maps while improving drive strength on late-arriving paths.
  5. 05
    Multi-Corner Sign-Off
    Final signoff ran 7 corners: SS/FF/TT at 0.9V/1.0V/1.1V, plus a process-skewed worst-case corner for the interface domain. All corners closed with positive setup margin before TSMC data freeze.

04Timing Closure: Numbers

The constraint rebuild, combined with targeted physical ECO, moved from 400+ failing endpoints to a clean signoff in 6 weeks — leaving 5 weeks for ICC package assembly, DRC/LVS closure, and TSMC submission.

•
400+ Failing Endpoints → 0
All setup and hold violations closed across 7 PVT corners. WNS reduced from -180ps to +22ps at the critical SS corner.
•
AOCV: 12% Pessimism Removed
Switching to depth-based AOCV removed systematic over-pessimism on characterized standard cell paths without relaxing actual timing discipline.
•
SI Integration: 40ps Recovered
Shielding and SI-aware routing on the 800MHz interface domain recovered 40ps average setup margin on the 20 most critical paths.
•
6 Weeks to Clean Signoff
From constraint rebuild to full multi-corner closure with 5 weeks of buffer remaining before TSMC shuttle data freeze.
Tape-out Coordination

05ICC Phase: TSMC Submission

TSMC 28nm ICC submission has additional requirements compared to mature nodes. The DFM rule deck, metal fill requirements, and ESD compliance checks added verification steps not present in our earlier 55nm experience.

  • •
    TSMC DFM Rule Deck

    Ran TSMC-provided DFM Calibre decks in addition to standard DRC. The high-density interface region required two rounds of metal fill adjustment to meet DFM density targets without disturbing routed connections.

  • •
    ESD Compliance

    Interface IO pads required ESD cell topology verification against TSMC 28nm IO guidelines. One pad configuration required redesign — caught during ICC pre-submission review, not in silicon.

  • •
    Engineering Query Response

    TSMC raised two engineering queries during ICC review: one on an antenna ratio at a high-fanout net, one on a via density concern in the interface region. Both resolved within 48 hours with targeted ECO.

  • •
    Data Package Assembly

    Assembled TSMC-format ICC package: GDS stream, LVS netlist, fill report, DRC waiver log, timing summary, and power analysis. Submitted 6 days ahead of shuttle window.

06Outcome

First-pass silicon success. The 800MHz interface met specification at all test corners. No re-spin required.

•
First-Pass Silicon
All interface performance targets confirmed on first silicon. 800MHz operation validated at full voltage range.
•
Shuttle Window Met
ICC package submitted 6 days before TSMC shuttle data freeze. No schedule risk to the shuttle.
•
Follow-on Engagement
Client re-engaged for next-generation 16nm design, citing timing closure discipline and TSMC ICC coordination as key factors.

07Lessons from 28nm Backend

Advanced node backend introduces variation modeling and SI complexity that isn't present at 55nm or 110nm. These lessons apply to any 28nm or below tapeout.

•
AOCV is Not Optional at 28nm
Global OCV derating creates systematic pessimism that masks real violations and generates false ones. AOCV or POCV with PDK-provided tables should be standard from day one.
•
SI Belongs in the Closure Loop
At 800MHz, coupling effects are not a post-route concern. They are a first-class timing variable that must be included in every ECO iteration.
•
Isolate High-Speed Clock Domains
Sharing CTS across domains with different clock frequencies creates skew budget conflicts. High-speed domains need dedicated clock trees with independent skew targets.
•
TSMC 28nm ICC Has Its Own Requirements
DFM deck compliance, ESD topology checks, and metal fill density targets add ICC steps that aren't documented in generic tapeout guides. Budget time for these.

References

  1. [1]
    TSMC 28nm Process Technology
    Taiwan Semiconductor Manufacturing Company
  2. [2]
  3. [3]

Knowledge Base

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