VLSIShuttle
VLSIShuttle Backend Team
IC Backend Execution Specialists
Feb 28, 20268 min read
Case Study

SMIC 40nm IoT SoC: Multi-Voltage Domain Backend and MPW Shuttle Coordination

Engineering postmortem on a SMIC 40nm IoT connectivity SoC with three independent power domains. How UPF-based implementation, voltage-aware signoff, and SMIC MPW shuttle scheduling were executed end to end — on schedule, first pass.

Discuss Your Backend Project
Background

01Project Context

An IoT connectivity SoC designed for low-power always-on operation with burst-mode RF transmission. Three distinct power domains with different supply rails, power-down sequencing requirements, and retention requirements.

The design used SMIC 40nm LP (low-power) process variant. Three voltage domains: a 1.1V always-on sensor management domain, a 1.0V main processing domain with power gating, and a 1.8V IO/RF interface domain operating at a different supply rail.

The client had a committed SMIC MPW shuttle slot 14 weeks out. The backend engagement started with a functionally-verified netlist and a UPF file that had never been verified against a physical implementation.

Implementation Risk

02Multi-Voltage Domain Challenges

Multi-voltage domain implementation at 40nm introduces physical and verification complexity that single-supply designs don't have. These were the specific risks we identified at engagement start.

  • •
    Level Shifter Placement

    Every signal crossing from the 1.0V domain to the 1.8V IO domain and vice versa required a level shifter insertion. The UPF specified where level shifters were needed logically but not where they should be physically placed to minimize routing congestion at domain boundaries.

  • •
    Isolation Cell Behavior

    Power-gated domains require isolation cells to clamp outputs to a defined state when the domain is off. Wrong isolation polarity or missing isolation on an output path causes X-propagation during power-up — a functional failure that is not caught by standard STA.

  • •
    Power-Up Sequencing in Physical

    The UPF specified the logical power-up order, but the physical power grid had to support the inrush current profile during sequencing without causing IR drop violations during power-on — a dynamic verification concern not captured in static signoff.

  • •
    Voltage-Aware STA

    Standard timing analysis runs at a single supply. With three supply rails, paths crossing domain boundaries needed to be timed with different supply assumptions for the launching and capturing flip-flops — a setup requiring explicit multi-supply STA.

Backend Execution

03Implementation Strategy

We structured the implementation to handle multi-voltage domain constraints as a first-class requirement from floorplan through signoff.

  1. 01
    Domain-Aware Floorplan
    Power domain boundaries defined first in the floorplan, before any placement. The 1.8V IO ring placed at the chip periphery to minimize level-shifter routing distance. Power switches for the gated domain clustered near the domain boundary for efficient control routing.
  2. 02
    Level Shifter Pre-Placement
    Level shifters pre-placed at domain crossing points before standard cell placement. This prevented the placer from creating routing detours and ensured crossing signals had dedicated routing channels.
  3. 03
    UPF-Driven Isolation Verification
    Ran formal UPF consistency checks before any physical implementation. Found three cases where the UPF isolation specification was ambiguous — resolved with the front-end team before they caused physical rework.
  4. 04
    Power Grid Per Domain
    Each domain got an independently routed power grid with its own strapping density target, calculated from domain-specific power analysis. The always-on domain got a denser grid than the power-gated domain to support continuous operation.
  5. 05
    Multi-Supply STA Setup
    Configured PrimeTime with separate supply specifications per domain. Cross-domain paths timed with worst-case supply combination: low supply on launch domain, high supply on capture domain (setup) and reversed for hold.

04Voltage-Aware Signoff

Standard signoff checks are not sufficient for multi-voltage designs. We ran an extended verification sequence that included power-domain-aware checks at each stage.

•
UPF vs. Physical Consistency
Formal check that every logical domain boundary in the UPF was correctly reflected in the physical netlist — level shifters present and correctly oriented, isolation cells in place, power switches connected.
•
Dynamic Power Analysis
Vectorless dynamic power analysis per domain to verify IR drop during power-up sequencing. The 1.0V main domain showed 8% voltage droop during initial power-on — resolved by adjusting power switch turn-on timing in the UPF.
•
Retention Cell Verification
The always-on domain contained retention flip-flops for state preservation during main domain power-off. Physical verification confirmed save/restore control routing was correct and met timing for the retention protocol.
•
Cross-Domain Path Coverage
Explicit path groups for all domain-crossing signals in STA, confirmed all paths had consistent multi-supply timing models. 14 paths initially flagged as improperly modeled — all corrected before signoff.
ICC Execution

05SMIC MPW Shuttle Coordination

SMIC MPW shuttle scheduling has specific data package requirements and a firm cutoff window. We managed the ICC submission process directly with SMIC as part of our scope.

  • •
    SMIC Design Rule Compliance

    Ran SMIC 40nm Calibre DRC deck including LP-specific checks for power switch cells and retention flip-flops. Two DRC violations found in the power switch tap cell — resolved with cell-level ECO in coordination with SMIC design team.

  • •
    MPW Die Area Verification

    Confirmed die area within allocated MPW slot dimensions before data freeze. SMIC requires exact die boundary coordinates in the ICC submission — verified against the shuttle allocation document.

  • •
    Multi-Voltage LVS

    LVS with power-domain-aware comparison. Standard LVS doesn't verify supply connectivity across domain boundaries. Used SMIC-qualified multi-supply LVS configuration to confirm all power connections were correctly represented.

  • •
    ICC Package and Submission

    Assembled SMIC MPW ICC package: GDS, LVS netlist, DRC report, power analysis summary, and shuttle questionnaire. Submitted 8 days ahead of SMIC data freeze. SMIC confirmed acceptance with no engineering queries.

06Outcome

First-pass silicon. All three power domains operated correctly through the power-up sequence. IoT connectivity functionality confirmed on silicon.

•
First-Pass Silicon Success
All power domains powered up correctly in sequence. No isolation or level shifter failures. Retention state preserved correctly across power cycles.
•
MPW Shuttle On Schedule
ICC submission 8 days before cutoff. No schedule risk to the SMIC MPW slot — critical given the shared nature of the wafer and the customer's committed delivery date.
•
Power Performance Confirmed
Always-on domain power consumption in silicon measured within 5% of simulated target. Power-gated domain leakage confirmed at specification.

07Lessons from Multi-Voltage Backend

Multi-voltage domain implementation introduces verification complexity that compound with each additional domain. These principles apply to any UPF-based design at 40nm or below.

•
Resolve UPF Ambiguity Before Physical
Formal UPF consistency checking before placement prevents physical rework. Ambiguous isolation specification discovered in physical implementation requires front-end change — expensive and schedule-threatening.
•
Domain Boundaries First in Floorplan
Power domain boundaries must be floorplanned before standard cell placement. Retroactive domain boundary adjustment after placement causes significant congestion and timing disruption.
•
Dynamic IR Drop During Power-Up
Static IR analysis doesn't capture power-up inrush. At 40nm, power switch configuration and turn-on sequencing need explicit dynamic analysis — IR droop during power-on can cause functional failure not visible in static signoff.
•
MPW Shuttle Has Fixed Cutoffs
SMIC MPW shuttle data freeze is hard. Buffer time for SMIC engineering query response (typically 48–72 hours per query) must be planned into the ICC schedule — not treated as contingency.

References

  1. [1]
    SMIC 40nm Process Technology
    Semiconductor Manufacturing International Corporation
  2. [2]
    IEEE Unified Power Format Standard
    IEEE Standards Association
  3. [3]

Knowledge Base

Complete MPW Shuttle GuideWhat is ASIC Design?ASIC Design Services OverviewWafer Fabrication ProcessHow Semiconductor Foundries WorkASIC Design Flow ExplainedMPW Cost & Pricing GuideChip Prototyping Methods