Execution Scope
從 PDK setup 到 mask submission。我們承接完整的 backend execution cycle — DRC/LVS closure、multi-corner signoff、foundry coordination 及 GDS handoff — 確保 silicon on schedule。
Shuttle Service
MPW Shuttle Coordination
管理從 process selection 到 GDS handoff 及 foundry acceptance 的完整 MPW slot lifecycle。客戶提供經 DRC/LVS-clean 的 netlist 或 GDSII，我們負責 PDK provisioning、pre-tapeout checks、slot registration 及 mask submission，涵蓋 TSMC、SMIC、GlobalFoundries 及 UMC 項目。
- Foundry 與 process node selection
- PDK provisioning 與 DRC deck setup
- GDS submission 與 pre-tapeout checks
- Reticle slot registration 與 mask coordinates
- Fabrication tracking 與 foundry liaison
- Die delivery 與 incoming inspection
Typical Deliverables: Foundry-accepted GDSII、diced die lot、optional bare-die or packaged delivery、tapeout acceptance confirmation
Foundry Agency
Tapeout Agency
直接對接 TSMC、SMIC、GlobalFoundries、UMC 及 HLMC 的 foundry coordination。負責 NDA execution、PDK licensing、multi-foundry price comparison 及 tapeout data freeze management，為缺乏 foundry 關係的工程團隊降低 coordination overhead。
- Foundry NDA 與 PDK licensing
- Multi-foundry quote 與 lead-time comparison
- Engineering change 與 ECO coordination
- Tapeout deadline 與 data freeze management
- IP protection 與 secure data transfer
- Wafer procurement 與 delivery coordination
Typical Deliverables: Signed foundry contract、tapeout approval confirmation、wafer lot delivery、OSAT coordination on request
Backend Implementation
IC Physical Implementation
從 synthesized netlist 到 GDSII-ready 的 physical implementation。涵蓋 multi-corner/multi-mode signoff、PDK compliance 及 design-for-yield。專案全程 NDA 保護，所有 deliverables 的完整 IP 於專案完成後歸還客戶。
- Floorplanning 與 power grid design
- Place and route（Cadence Innovus / Synopsys ICC2）
- Multi-corner, multi-mode timing signoff
- DRC/LVS closure 與 antenna rule check
- Parasitic extraction 與 SI analysis
- GDSII generation 與 tapeout package prep
Typical Deliverables: Signoff-clean GDSII、timing/power/SI reports、LVS netlist、DRC-clean layout、foundry submission package
Execution Experience
8
Tapeout deliveries（近 24 個月）
22–180nm
Node coverage
0
Silicon failures
10–14 wk
Typical backend cycle
Representative Tapeout Work
- —28nm TSMC — 1.8M-instance mixed-signal SoC，6 clock domains，800MHz SerDes interface
- —55nm SMIC — Sensor AFE with 12-bit ADC，OCV derating rebuild，first-pass silicon
- —40nm SMIC — IoT SoC，3 voltage domains，UPF-based implementation
- —28nm ECO — 130-register scan chain insertion post-route，no full rerun