IC Backend Execution 與 Tapeout 責任交付
提供 Netlist-to-GDSII implementation，涵蓋 Timing Closure、DFT integration，以及跨主要 foundry 的 tapeout coordination。
支援於多家主要 foundry 進行 tapeout，包括 TSMC、SMIC、UMC 與 Tower
Execution Scope
我們實際負責的範圍
不拆分、不外包。單一專責 backend 團隊端到端執行。
01 Backend Implementation
Netlist handoff → signoff-ready GDSII
- Multi-corner signoff
- DRC/LVS closure
- IR/EM validation
- STA 與 physical verification
02 Tapeout & ICC Interface
GDS freeze → foundry-accepted mask
- PDK integration
- MPW coordination
- Mask package assembly
- Foundry submission and acceptance
03 ECO & Silicon Assurance
Late-stage changes → incremental re-signoff
- Incremental re-signoff
- Late-stage timing control
- Post-layout validation
- Silicon debug support
Execution Record
8
Tapeout deliveries（近 24 個月）
22–180nm
Node coverage
3
Repeat clients
10–14 wk
Typical backend cycle
Representative Tapeout Work
- —28nm TSMC — 1.8M-instance mixed-signal SoC，6 clock domains，800MHz timing-critical SerDes interface，45 signoff corners
- —55nm SMIC — Sensor AFE with embedded 12-bit ADC，OCV derating rebuild across analog/digital PVT corners，first-pass silicon
- —110nm UMC — Analog-dominant power management controller，full-custom analog block integration with digital wrapper
- —40nm SMIC — IoT connectivity SoC，3 independent voltage domains，UPF-based implementation with voltage-aware signoff
- —28nm ECO — 130-register scan chain insertion post-route，incremental signoff without full P&R rerun，one-week buffer to shuttle
ICC Responsibility
與一般 Design Team 的差異
多數 backend 團隊在 signoff 後即視為結案。我們負責 foundry interface 的全程管理直到 GDS acceptance。
- →Submission-ready DRC/LVS
- →MPW shuttle scheduling
- →Mask data preparation
- →GDS acceptance confirmation
Case Study
SMIC 55nm — Sensor AFE with Embedded ADC
Situation
Mixed-signal AFE 含 embedded 12-bit ADC。客戶因先前 backend 合作在跨溫度角 timing 持續失敗及首次 silicon 失敗後終止合作。距 SMIC shuttle 截止僅剩 9 週。
What we did
識別到 timing violation 根因為 mixed-signal path 的 OCV derating 不足。重建 constraint set，為 analog 與 digital domain 分設獨立 PVT corner。每個 ECO cycle 後完成 incremental re-signoff。ICC package 提前組裝並提交，保留一週 buffer。
Outcome
First-pass silicon success。所有 analog performance target 於 silicon 上達成。客戶追加 28nm follow-on project。
討論 Tapeout Scope
提供 node、schedule 及 scope，48 小時內回覆初步技術評估。