IC Backend Execution 與 Tapeout Delivery
Netlist-to-GDSII implementation，包含 timing closure、DFT integration 及跨 TSMC、Samsung、SMIC、UMC 等主要 foundry 的 tapeout coordination。
從 netlist handoff 到 foundry acceptance 的 tapeout ownership
3nm – 180nm · TSMC / Samsung / UMC / SMIC · Mixed-signal · Multi-domain · ECO-ready
Tapeout experience across TSMC, Samsung, UMC and SMIC
Execution Responsibility
我們作為單一 accountable team 負責 backend execution 與 tapeout readiness。
01 Implementation
Netlist handoff → signoff-ready GDSII
- Floor planning & power grid
- Place & Route execution
- Clock Tree Synthesis
- Multi-corner timing closure
02 Signoff
Verification → foundry submission readiness
- DRC/LVS closure
- IR/EM validation
- Multi-corner STA
- Physical verification signoff
03 Tapeout Coordination
GDS freeze → mask acceptance
- PDK compliance validation
- Foundry submission package
- MPW shuttle coordination
- GDS acceptance confirmation
Execution Record
8+
Tapeout deliveries
3nm–180nm
Node coverage
3+
Repeat clients
10–14 wk
Typical backend cycle
Representative Tapeout Work
- TSMC 28nm1.8M-instance mixed-signal SoC，6 clock domains，800MHz timing-critical SerDes interface，45 signoff corners
- SMIC 55nmSensor AFE with embedded 12-bit ADC，OCV derating rebuild across analog/digital PVT corners，first-pass silicon
- UMC 110nmAnalog-dominant power management controller，full-custom analog block integration with digital wrapper
- SMIC 40nmIoT connectivity SoC，3 independent voltage domains，UPF-based implementation with voltage-aware signoff
團隊通常在哪裡出問題
- —Backend ownership 分散
- —Timing closure 延遲到後期才處理
- —Tapeout 由缺乏 context 的第三方處理
- —ECO 缺乏 physical awareness
我們執行並負責從 implementation 到 tapeout acceptance 的完整 flow。
Case Study
SMIC 55nm — Sensor AFE with Embedded ADC
緊迫時程下交付，first-pass silicon success
Situation
Mixed-signal AFE 含 embedded 12-bit ADC。客戶因先前 backend 合作在跨溫度角 timing 持續失敗及首次 silicon 失敗後終止合作。距 SMIC shuttle 截止僅剩 9 週。
What we did
識別到 timing violation 根因為 mixed-signal path 的 OCV derating 不足。重建 constraint set，為 analog 與 digital domain 分設獨立 PVT corner。每個 ECO cycle 後完成 incremental re-signoff。ICC package 提前組裝並提交，保留一週 buffer。
Outcome
First-pass silicon success。所有 analog performance target 於 silicon 上達成。客戶追加 28nm follow-on project。
討論您的 Scope
提供 node、schedule 及 scope，我們於 48 小時內回覆 feasibility 與 execution plan。