The Complete Guide to Multi Project Wafer (MPW) Services

01What is Multi Project Wafer (MPW)?

Multi Project Wafer (MPW), sometimes called MPW shuttle or multi-project wafer service, is a semiconductor fabrication approach where multiple independent chip designs from different customers are placed on a single wafer for manufacturing. This shared-cost model makes custom IC development accessible to startups, universities, and companies with limited prototyping budgets.

How MPW Works

In a multi project wafer run, the semiconductor foundry combines designs from 10-50+ different customers onto a single reticle. Each design occupies only the silicon area it needs, and the mask and fabrication costs are divided among all participants proportionally.

MPW vs Full-Mask Production

While full-mask (dedicated wafer) fabrication gives you complete control, it requires purchasing an entire mask set and wafer lot. Multi project wafer services let you share these fixed costs, reducing expenses from millions of dollars to as low as $10,000-$50,000 depending on the process node.

Industry Standard Practice

MPW shuttles have been an industry standard since the 1980s. Major foundries like TSMC, GlobalFoundries, SMIC, and UMC all offer multi-project wafer programs, making advanced process technologies accessible to innovators worldwide.

02Cost and Risk Characteristics

Multi-project wafer services provide cost-shared foundry access for silicon prototyping and design validation. Structural characteristics of the MPW model:

• •
  Shared mask cost model

  NRE is distributed across multiple designs on a single reticle. Participating designs pay for silicon area used, not full mask set cost.

• •
  Availability of production process nodes

  MPW programs exist at mature (180nm–65nm), mainstream (55nm–28nm), and advanced (22nm–7nm) nodes via TSMC, SMIC, GlobalFoundries, and UMC.

• •
  Silicon validation prior to volume commitment

  Fabricated die enables electrical characterization, timing validation, and analog performance measurement before full-mask investment.

• •
  Scheduled shuttle cadence

  Most foundry MPW programs run on fixed quarterly or bi-monthly schedules. Participation requires registration before the data freeze deadline.

• •
  Die count constraints

  A standard MPW slot yields 10–100 known good dies, determined by purchased area and process yield. Volume production requires dedicated wafer runs.

• •
  IP block validation in fabricated silicon

  Standard cell libraries, memory macros, and analog IP can be characterized in actual silicon before integration into production SoC designs.

03MPW Shuttle Process Flow

The multi project wafer fabrication process follows these key steps from design submission to chip delivery.

1. 01
   Design Preparation

   Complete your GDSII/OASIS layout files and ensure they pass all DRC/LVS checks for your target process. Prepare I/O pad frame and follow the foundry's design rules.
2. 02
   Shuttle Selection

   Choose your foundry and process node based on your design requirements. Review the MPW shuttle calendar for upcoming tapeout deadlines and select a run that fits your schedule.
3. 03
   Quote & Registration

   Submit your die size and required quantity. Receive a multi project wafer price quote based on your selected node and area. Complete registration and payment to secure your slot.
4. 04
   GDS Submission

   Submit your final GDSII files before the tapeout deadline. The foundry or shuttle organizer performs final verification and integrates your design into the shared reticle.
5. 05
   Fabrication

   Your design enters the foundry fab along with other MPW participants. Standard wafer fabrication takes 8-16 weeks depending on the process complexity and foundry queue.
6. 06
   Dicing & Delivery

   After fabrication, wafers are diced to separate individual dies. Your chips are packaged (if requested) and delivered to you for testing and characterization.

04MPW Cost Reference

Indicative cost ranges by process node. Actual pricing depends on die size, foundry, number of dies, and packaging. Contact foundry programs or shuttle coordinators for confirmed quotes.

• •
  Primary cost variables: Die size (mm²), process node, number of dies, packaging type (bare die vs. packaged).
• •
  Area optimization: Floorplan compaction directly reduces cost. Pad ring sharing between variants is possible on some programs.
• •
  Node selection for analog/mixed-signal: Mature nodes (180nm–90nm) provide adequate performance for most analog front-ends at significantly lower NRE than advanced nodes.

05Process Node Reference

MPW programs are available across a range of CMOS process generations. Node selection is determined by design requirements, not cost alone.

• •
  Mature nodes: 180nm – 90nm

  Analog, HV, power management, sensor AFE, and mixed-signal applications. Lower NRE. Foundry support from SMIC, UMC, Tower, HHGrace.

• •
  Mainstream nodes: 65nm – 40nm

  Mixed-signal SoCs, wireless connectivity, MCU, and consumer digital. Broad PDK ecosystem. Available via TSMC, SMIC, GlobalFoundries.

• •
  Advanced nodes: 28nm – 16nm

  High-density digital, application processors, AI inference. Requires full DFM compliance. TSMC and GlobalFoundries primary shuttle programs.

• •
  Specialty processes

  BCD (power electronics), RF CMOS / mmWave, SiGe BiCMOS (high-frequency), SOI (radiation tolerance). Availability varies by foundry and quarter.

06Multi Project Wafer FAQ

Frequently asked questions about MPW shuttle services and multi-project wafer fabrication.

What is a multi project wafer (MPW)?

A Multi Project Wafer (MPW) is a semiconductor fabrication service where multiple different chip designs from various customers are placed on the same silicon wafer. This shared manufacturing approach significantly reduces the cost per design because mask costs, wafer processing costs, and other fixed expenses are divided among all participants. MPW is also commonly called 'shuttle service' or 'prototyping run'.

How much does multi project wafer service cost?

Multi project wafer cost varies widely based on the process node and die size. For mature nodes (180nm-65nm), expect $10,000-$50,000 for small-to-medium designs. Mainstream nodes (55nm-28nm) typically range from $30,000-$150,000. Advanced nodes (16nm and below) can cost $100,000 to over $500,000. Use our online calculator for an estimate specific to your requirements.

How long does MPW shuttle fabrication take?

The typical MPW turnaround time is 8-16 weeks from GDS submission to chip delivery. This includes time for reticle assembly, wafer fabrication, testing, dicing, and packaging (if requested). Advanced nodes generally take longer due to more complex processing steps. Always check the shuttle calendar for specific run schedules.

What's the difference between MPW and full-mask production?

In MPW, you share wafer space with other designs and receive a limited number of chips (typically 10-100 dies). In full-mask production, you own the entire reticle and receive complete wafer lots (25+ wafers with thousands of dies). MPW is ideal for prototyping and small volumes; full-mask is for mass production. MPW typically costs 1/10th to 1/100th of full-mask runs.

What process nodes are available for MPW?

Multi project wafer services are available across a wide range of nodes: from legacy 350nm/250nm for specialized applications, through mature 180nm-65nm for analog/mixed-signal, mainstream 55nm-28nm for balanced performance, to advanced 22nm-7nm for high-performance digital. Major foundries like TSMC, SMIC, GlobalFoundries, and UMC offer regular MPW shuttles.

Can I get packaged chips from MPW runs?

Yes, most MPW services offer packaging options. You can receive bare dies (unpackaged) for your own assembly, or request standard packages like QFN, QFP, BGA, or custom packaging. Packaging adds cost and time but is essential if you need to test chips on standard PCBs or deliver to end customers.

How many chips do I get from an MPW run?

The number of dies depends on your purchased area and die yield. Typically, customers receive 10-100 known good dies from an MPW shuttle. If you need more chips, you can purchase additional area in the same run or consider a dedicated wafer run for higher quantities.

Is MPW suitable for commercial products?

MPW is primarily designed for prototyping, but it can serve low-volume commercial production (hundreds to thousands of chips annually). For higher volumes, transitioning to full-mask production is more economical. Many companies use MPW for initial product launches and customer sampling before scaling to volume production.

• 22nm – 180nm process nodes
• Mixed-signal and digital backend
• MPW and dedicated mask engagement
• ICC coordination and foundry submission
• Multi-corner signoff
• NDA-protected engagements

Discuss MPW Scope

Send node, die size estimate, and schedule. Initial response within 48 hours.

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   TSMC Multi-Project Wafer (MPW) Service

   Taiwan Semiconductor Manufacturing Company
2. [2]
   Europractice IC Service

   IMEC - Europractice
3. [3]
   MOSIS Integrated Circuit Fabrication Service

   USC Information Sciences Institute
4. [4]
   Semiconductor Industry Association Reports

   SIA