TSMC 90nmMPW Shuttle Service
Get professional tapeout services for TSMC 90nm through VLSIShuttle. We offer competitive pricing, reliable delivery, and end-to-end technical support.
MPW Price Range
$12,000 - $35,000
*Based on EUROPRACTICE 2025 public data. Actual pricing may vary.
Lead Time
12-16 weeks
Variants
2
Upcoming
1
⚠️ Price Disclaimer: The ranges above are based on EUROPRACTICE 2025 public data. Actual 2026 pricing may change at any time due to exchange rate fluctuations, process revisions, and capacity factors. For accurate pricing, please contact VLSIShuttle or contact the foundry directly.
Upcoming Shuttle Schedule
| Foundry | Process | Deadline | Est. Delivery | Status | |
|---|---|---|---|---|---|
| TSMC | 90nm | 2026-03-13 | 2026-06-11 | Open | Apply |
About TSMC
Taiwan Semiconductor Manufacturing Company (TSMC) is the world's largest dedicated semiconductor foundry, headquartered in Hsinchu, Taiwan. Founded in 1987, TSMC pioneered the pure-play foundry business model and has since become the technology leader in advanced process nodes. TSMC offers a comprehensive range of process technologies from mature nodes (180nm, 130nm, 90nm) to cutting-edge advanced nodes (7nm, 5nm, 3nm). Their MPW (Multi-Project Wafer) shuttle service provides cost-effective prototyping solutions for IC design companies of all sizes. Key advantages of TSMC MPW service: - Industry-leading yield rates and quality control - Extensive IP ecosystem and design enablement - Global customer support and technical assistance - Flexible scheduling with multiple shuttle runs per year TSMC's mature process nodes (65nm and above) are particularly popular for analog, mixed-signal, power management, and automotive applications due to their proven reliability and competitive pricing.
Key Advantages
- Industry-leading yield rates (typically >95%)
- Extensive IP ecosystem with 10,000+ silicon-proven IPs
- Global technical support
- Multiple shuttle schedules throughout the year
90nm Process Technology
The 90nm node bridges mature and advanced process technologies, offering significant density and performance improvements. It is popular for applications requiring more digital integration while maintaining reasonable costs. 90nm provides approximately 2x the transistor density of 130nm and is commonly used for automotive processors, consumer SoCs, and industrial applications.
Typical Applications
Frequently Asked Questions
How to Start a TSMC 90nm MPW Tapeout
- 1
Confirm Design Requirements
Verify your design is compatible with 90nm: operating voltage, minimum feature size, IP compatibility, and target performance specs.
- 2
Request a Quote
Submit a project brief to VLSIShuttle including die area (mm²), quantity needed, and target delivery date. Receive a quote within 24 hours.
- 3
Sign Agreements & Obtain PDK
After signing an NDA and service agreement, we help you apply for the TSMC 90nm PDK to begin physical design.
- 4
Complete Design and Pass DRC/LVS
Finish RTL, synthesis, place & route, and ensure your GDSII passes foundry DRC/LVS checks before tapeout submission.
- 5
Submit GDSII and Await Fabrication
Submit your GDSII before the shuttle deadline. TSMC merges your design with others for wafer manufacturing. Typical lead time: 12-16 weeks.
- 6
Receive Dies and Test
Receive diced dies (typically 20–100), then perform functional testing and characterization to validate your design meets target specifications.
Typical Shuttle Cadence (2026 Reference Structure)
Most foundry MPW programs run on a quarterly cadence, with 3–4 shuttles per calendar year per process node. The general sequence from design freeze to die delivery follows a predictable structure, though exact dates are set by the foundry and must be confirmed with the shuttle coordinator.
- Submission freeze: Design data lock, typically 2–4 weeks before fab start. No GDS changes are accepted after this point under standard shuttle terms.
- Mask set completion: The foundry prepares a combined mask set from all participating designs. This phase runs 2–4 weeks after freeze.
- Fab start to wafer out: Wafer processing runs 10–14 weeks depending on node complexity. Advanced nodes (16nm and below) typically run closer to 14 weeks.
- Die delivery: Wafers are diced, inspected, and shipped. Total cycle from submission freeze to die receipt: 12–18 weeks for mature nodes, 16–22 weeks for advanced nodes.
For confirmed TSMC 90nm shuttle dates in 2026, refer to the TSMC MPW Schedule 2026. To estimate mask and wafer cost per mm² across nodes, the DPW cost calculator provides per-node reference data for budget planning.
All timelines are reference estimates based on typical program cadence. Actual dates are set by the foundry and subject to change. Confirmed deadlines must be obtained from VLSIShuttle or the foundry shuttle coordinator.
Submission Considerations
- DRC/LVS clean before freeze: Design rule and layout-versus-schematic checks must pass against the foundry-provided PDK ruleset before the shuttle freeze date. Most MPW programs do not accept post-submission rule fix requests.
- PDK version alignment: Confirm which PDK revision applies to the target shuttle. DRC interpretation differences between PDK versions are common; using an outdated or mismatched PDK can produce false-clean results.
- IP license validation: All third-party IP blocks must be licensed for the target foundry and process node prior to tapeout submission. License scope (prototype, production, or both) should be documented before freeze.
- GDS layer mapping: The submitted GDS must conform to the shuttle's layer definition file (LDF). Layers not recognized in the LDF are typically stripped without warning; verify the complete layer map before final export.
- Mask cost allocation: MPW pricing is based on gross die area (mm²), which includes seal ring overhead and keep-out zones. Designs with large exclusion regions should account for this in area budgeting.
- Wafer acceptance policy: Foundry wafer acceptance tests (WAT) are run after wafer-out. Under standard MPW agreements, a failing WAT site monitor does not automatically trigger a rework commitment. Review the program's yield guarantee terms before committing.
Backend Integration Notes
Transition constraints should not be relaxed at the final pre-tapeout signoff stage. Violations masked by OCV or AOCV derating may not appear in pre-silicon timing analysis but can manifest as yield-limiting paths post-silicon.
Delay cell insertion for hold fixing near the shuttle freeze deadline introduces risk. Cells added without full STA re-convergence across all corners can alter inter-stage timing relationships under process variation.
Mixed-signal designs require clock domain crossings to be explicitly constrained as false paths or multi-cycle paths. Untreated CDCs are a common source of functional failures not visible in pre-silicon digital simulation.
Late ECO changes in the final week before freeze should be limited to minimum-impact metal-only edits. Poly-layer or diffusion changes at this stage generally cannot be re-verified against all extraction corners within the available window.
Submit your project requirements and our experts will contact you within 24 hours.
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Data Sources
Price ranges, process node specifications, and shuttle schedules on this page are sourced from the following authoritative references. All data is for reference only; actual pricing is subject to final confirmation.
IMEC – EUROPRACTICE · Primary source for MPW price ranges (2025 public rates, EUR/mm², converted to USD)
TSMC · Process technology specifications and shuttle schedules
USC Information Sciences Institute · Industry reference pricing and tapeout service standards
Semiconductor Industry Association · Industry data and market analysis
Ready to Start Your TSMC 90nm Project?
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